NXP Semiconductors UJA1131AHW/3F0/0Y
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- UJA1131AHW/3F0/0Y
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- NXP Semiconductors
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UJA1131AHW/3F0/0Y.pdf
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- UJA1131AHW/3F0/0Y
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Product details
Overview
UJA1131AHW/3F0/0Y from NXP Semiconductors is an automotive System Basis Chip (SBC) integrating a buck-boost SMPS, 3.3 V/500 mA LDO (V1), 5 V/100 mA auxiliary regulator (V2), HS-CAN transceiver compliant with ISO 11898-2:201x and CAN FD up to 2 Mbit/s, dual LIN 2.x transceivers, and four configurable HVIOs - all in a single HTQFP48 package. It enables fail-safe ECU power management, limp-home functionality, and battery voltage monitoring for engine control modules.
For engineers reviewing the UJA1131AHW/3F0/0Y datasheet, UJA1131AHW/3F0/0Y pinout, UJA1131AHW/3F0/0Y application, or UJA1131AHW/3F0/0Y equivalent, this device serves as a complete power-and-communication hub for automotive ECUs requiring robust low-voltage operation (down to 2 V), partial networking support, and SPI-configurable safety features.
Technical Context
The UJA1131AHW/3F0/0Y implements a fully autonomous buck-boost SMPS with automatic mode selection, delivering regulated output to V1 and optionally V2 while supporting pass-through mode for minimal quiescent current. Its CAN transceiver meets ISO 11898-2:201x and supports CAN FD data-field speeds up to 2 Mbit/s with loop-delay symmetry compliance.
This variant includes two LIN transceivers (LIN1/LIN2), four HVIOs configurable as high-side/low-side drivers or wake-up inputs, and a 10-bit A/D converter for dual-channel battery monitoring (BAT/BATSENSE). All configuration-including limp-home behavior, watchdog window timing, and sleep-mode enable-is stored in non-volatile memory.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| V1 Output | 3.3 V ±2 %, 500 mA - powers microcontroller with transient load capability and undervoltage reset at selectable thresholds |
| V2 Output | 5 V ±2 %, 100 mA - configurable as sensor supply with short-to-battery/ground protection and loss-of-ground immunity |
| CAN Data Rate | Up to 2 Mbit/s in CAN FD data field - enables high-speed diagnostics and firmware updates over CAN bus |
| LIN Compliance | LIN 2.x and SAE J2602 - supports dual independent LIN networks with integrated slave termination |
| SMPS Mode | Automatic buck/boost switching - sustains V1 operation down to 2 V battery input without external semiconductors |
| HVIO Count | 4 pins - individually configurable as HS/LS drivers or wake-up inputs with open-load/short-circuit diagnostics |
| Package | HTQFP48 (10 mm × 10 mm, exposed pad) - enables efficient thermal dissipation in compact ECU layouts |
Pinout & Package
UJA1131AHW/3F0/0Y is housed in a 48-pin HTQFP package with thermally enhanced exposed die pad connected internally to GND. The pinout supports full system integration: dedicated BAT, V1, V2, CANH/CANL, LIN1/LIN2, SPI (SDI/SDO/SCK/SCSN), dual interrupt outputs (INTN1/INTN2), RSTN, EN, LIMP, four HVIOs (HVIO1–HVIO4), and SMPS interface (BATSMPS, L1, L2, VSMPS, BOOTH1/BOOTH2, CAPA/CAPB).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| V1 | Main microcontroller supply output | 3.3 V regulated output with 500 mA capability and clamp protection limiting voltage to ≤6 V under reverse current |
| VCAN | CAN transceiver supply | 5 V dedicated supply for HS-CAN physical layer - isolates CAN noise from core logic rails |
| RXDC / TXDC | CAN data interface | Differential receive/transmit signals compatible with ISO 11898-2:201x and CAN FD fast-phase timing |
| LIN1 / LIN2 | LIN bus interfaces | Two independent LIN physical layers supporting SAE J2602 and downward-compatible with LIN 1.3 |
| HVIO1–HVIO4 | Configurable high-voltage I/O | Each supports HS/LS driving, wake-up input, or limp-home output (HVIO2–HVIO4) with diagnostics and loss-of-ground proofing |
| INTN1 / INTN2 | Interrupt outputs | INTN1 reports all events; INTN2 reserved for high-priority alerts (e.g., overtemperature, V1 undervoltage) |
| RSTN | Bidirectional reset | Active-low reset line referenced to V1 - triggered by watchdog overflow or V1 undervoltage |
| LIMP | Limp-home activation signal | Drives external hardware during critical failure; configurable via non-volatile memory for static or pulsed output |
Key Features
| Feature | Design Value |
|---|---|
| Buck-boost SMPS with single coil | Eliminates need for external MOSFETs/diodes; enables operation at battery voltages as low as 2 V while maintaining V1 regulation |
| Dual LIN + HS-CAN transceivers | Reduces BOM count and PCB area vs. discrete transceivers; supports concurrent LIN diagnostics and CAN FD communication |
| Four diagnostic HVIOs | Provides direct control of solenoids, relays, or sensors with built-in open-load detection, short-circuit protection, and wake-up edge/threshold configuration |
| Non-volatile configuration memory | Allows factory programming of limp-home behavior, watchdog timing, sleep-mode enable, and voltage thresholds - no runtime reconfiguration required |
| ISO 7637-3 transient protection | Withstands automotive load-dump and jump-start transients on BAT, CAN, and LIN pins without external TVS devices |
Applications
| Engine Control Unit (ECU) | Body Control Module (BCM) |
|---|---|
Use Scenario: Real-time engine timing, fuel injection, and emissions control in gasoline/diesel powertrains. IC Role / Device Role / Timing Role: Central SBC providing regulated 3.3 V power to MCU, CAN FD communication for OBD-II diagnostics, dual LIN for throttle/valve actuators, and HVIO-driven ignition coil control. Use Value: Maintains MCU operation during cranking (2–6 V battery dips) via boost mode; enables CAN FD firmware updates at 2 Mbit/s without bus interruption. | Use Scenario: Centralized lighting, door lock, window lift, and HVAC control in modern vehicle architectures. IC Role / Device Role / Timing Role: Power manager and communication hub interfacing MCU with CAN backbone and multiple LIN subnets (e.g., mirror, seat, climate nodes). Use Value: Dual LIN transceivers eliminate need for external LIN ICs; HVIOs directly drive LED drivers and relay coils with diagnostics, reducing external component count. |
| Advanced Driver Assistance Systems (ADAS) Sensor Hub | Electric Power Steering (EPS) ECU |
Use Scenario: Aggregation and preprocessing of radar, camera, and ultrasonic sensor data before transmission to domain controller. IC Role / Device Role / Timing Role: SBC supplying 3.3 V to vision processor, managing CAN FD sensor fusion data, and using HVIOs for sensor biasing/wake-up signaling. Use Value: Battery monitoring and limp-home outputs ensure fail-operational behavior during voltage sags; CAN FD passive partial networking prevents spurious wake-ups during ADAS bus traffic. | Use Scenario: High-reliability motor control for steering assist with torque feedback and fault containment. IC Role / Device Role / Timing Role: Safety-critical SBC delivering 3.3 V to ASIL-B MCU, enabling CAN FD real-time torque commands, and asserting LIMP signal to mechanical fallback path on failure. Use Value: Integrated watchdog with window mode and non-volatile configuration ensures deterministic reset behavior; EN pin allows safe shutdown of motor driver on MCU fault. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar automotive SBC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| UJA1132HW/3V3 | Same buck-boost SMPS, 3.3 V/500 mA V1, dual LIN, 4 HVIOs - differs only in non-volatile memory configuration defaults (e.g., limp-home settings, watchdog timeout) | No functional difference in hardware; intended for same ECU designs where factory-programmed defaults differ | Select UJA1132HW/3V3 if default NVM settings better match target application's limp-home or wake-up requirements |
| TLE9471-3ES | Single LIN (not dual), no CAN FD support, 3.3 V/500 mA V1, 8 HVIOs - uses different SMPS architecture (buck-only with external boost for low-VBAT) | Suitable for cost-sensitive LIN-centric ECUs without CAN FD needs; higher HVIO count but lacks CAN FD partial networking | Choose TLE9471-3ES when dual LIN and CAN FD are unnecessary and higher HVIO count is prioritized over CAN FD speed and partial networking |
Compared with UJA1132HW/3V3, UJA1131AHW/3F0/0Y offers identical hardware but distinct factory-programmed NVM defaults; versus TLE9471-3ES, it provides native CAN FD support and dual LIN at the expense of fewer HVIOs, making it optimal for CAN FD–based ECU architectures requiring LIN peripheral control.
Availability
UJA1131AHW/3F0/0Y is available at Aetrix Electronics and suitable for engine control units, body control modules, ADAS sensor hubs, and electric power steering ECUs requiring stable component supply across automotive production lifecycles.
Supply support for UJA1131AHW/3F0/0Y includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader focused on secure connectivity solutions for automotive, industrial, and IoT applications, with deep expertise in automotive electronics and functional safety.
The UJA113x product line was designed specifically for next-generation automotive ECUs needing integrated power management, CAN FD communication, and fail-safe diagnostics - targeting ASIL-B–compliant systems with reduced BOM and layout complexity.
FAQ
What is the minimum battery voltage at which UJA1131AHW/3F0/0Y can sustain 3.3 V output to the microcontroller?
UJA1131AHW/3F0/0Y maintains regulated 3.3 V output down to 2 V battery input using its integrated boost function. This capability is confirmed in the datasheet Section 2.2 and enables uninterrupted MCU operation during cold-cranking events typical in automotive applications.
Does UJA1131AHW/3F0/0Y support CAN FD partial networking with CAN FD-passive wake-up?
No - UJA1131AHW/3F0/0Y does not support CAN FD partial networking or CAN FD-passive wake-up. That feature is exclusive to UJA113xFD/x variants (e.g., UJA1131HW/FD/3V/4). UJA1131AHW/3F0/0Y implements full CAN FD active communication up to 2 Mbit/s but lacks selective wake-up filtering for CAN FD traffic.
How many LIN transceivers does UJA1131AHW/3F0/0Y integrate, and are they independently configurable?
UJA1131AHW/3F0/0Y integrates two fully independent LIN 2.x transceivers (LIN1 and LIN2), each with dedicated RXDL/TXDL pins and compliant with SAE J2602. They support separate baud rates, node addressing, and diagnostic protocols - confirmed in Table 1 and Section 2.5 of the datasheet.
Can the four HVIOs on UJA1131AHW/3F0/0Y be used simultaneously as high-side drivers and wake-up inputs?
No - each HVIO (HVIO1–HVIO4) is individually configurable either as a high-side/low-side driver or as a wake-up input, but not both simultaneously. Configuration is controlled via SPI registers and non-volatile memory, with diagnostics (open-load, short-circuit) active in driver mode and edge/threshold programmability in wake-up mode.
What is the purpose of the LIMP pin on UJA1131AHW/3F0/0Y, and how is its behavior configured?
The LIMP pin on UJA1131AHW/3F0/0Y activates external 'limp-home' hardware during critical failures. Its output behavior (static high-side, 100 Hz/10 % duty, or 1.25 Hz/50 % duty) is configured via non-volatile memory and can be set independently for HVIO2, HVIO3, and HVIO4 - as specified in Section 2.6 and Table 1 of the UJA113x datasheet.
UJA1131AHW/3F0/0Y Specifications
- Product attributes
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- NXP Semiconductors
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- Bulk
- Product Status:
- Active
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UJA1131AHW/3F0/0Y FAQ
1.How can I place an order for UJA1131AHW/3F0/0Y through Aetrix?
Please submit a Request for Quotation (RFQ) for UJA1131AHW/3F0/0Y on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for UJA1131AHW/3F0/0Y reliable?
The price and inventory of UJA1131AHW/3F0/0Y are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for UJA1131AHW/3F0/0Y is usually 5 days.
3.What payment methods are accepted for UJA1131AHW/3F0/0Y?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for UJA1131AHW/3F0/0Y transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for UJA1131AHW/3F0/0Y?
UJA1131AHW/3F0/0Y orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your UJA1131AHW/3F0/0Y order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for UJA1131AHW/3F0/0Y?
For technical support, including UJA1131AHW/3F0/0Y datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your UJA1131AHW/3F0/0Y requirements.
6.How does Aetrix verify that UJA1131AHW/3F0/0Y is sourced from the original manufacturer or authorized distributors?
All UJA1131AHW/3F0/0Y products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that UJA1131AHW/3F0/0Y meets industry standards.
7.What is the process for return or replacement of UJA1131AHW/3F0/0Y?
All UJA1131AHW/3F0/0Y units undergo pre-shipment inspection (PSI). If there is an issue with UJA1131AHW/3F0/0Y, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The UJA1131AHW/3F0/0Y part is unused and in its original packaging.
Return procedure for UJA1131AHW/3F0/0Y:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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