NXP Semiconductors UJA1132AHW/5F0/0Y
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- UJA1132AHW/5F0/0Y
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- NXP Semiconductors
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UJA1132AHW/5F0/0Y.pdf
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Product details
Overview
UJA1132AHW/5F0/0Y from NXP Semiconductors is a buck/boost System Basis Chip (SBC) for automotive ECUs, integrating a 5 V/500 mA LDO (V1), HS-CAN transceiver compliant with ISO 11898-2:201x and CAN FD up to 2 Mbit/s, dual LIN 2.x transceivers, and a switch-mode power supply supporting operation down to 2 V battery input. It delivers fail-safe microcontroller supply, battery monitoring, watchdog, limp-home outputs, and SPI-based configuration via non-volatile memory - deployed in engine control, body electronics, and ADAS domain controllers.
For engineers reviewing the UJA1132AHW/5F0/0Y datasheet, UJA1132AHW/5F0/0Y pinout, UJA1132AHW/5F0/0Y application, or UJA1132AHW/5F0/0Y equivalent, this page provides verified technical context, exact pin functions, real-world automotive use cases, and validated alternative parts for ECU power and communication subsystem design.
Technical Context
The UJA1132AHW/5F0/0Y implements a fully autonomous buck-boost SMPS with automatic mode selection, enabling uninterrupted microcontroller supply during battery dips as low as 2 V. Its CAN transceiver supports active CAN FD communication at up to 2 Mbit/s in the data field while maintaining ISO 11898-2:201x timing compliance.
This variant includes dual LIN transceivers compliant with SAE J2602 and LIN 2.x, two-channel battery voltage monitoring with 10-bit ADC (±300 mV accuracy), and four configurable HVIOs supporting high-side/low-side drive or wake-up input roles - all managed via 16-/24-/32-bit SPI interface with non-volatile configuration storage.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| V1 Output | 5 V ±2 %, 500 mA - powers MCU core with undervoltage reset at selectable 60–90 % threshold |
| SMPS Mode | Buck/Boost auto-switching - sustains V1 during battery dips to 2 V without external semiconductors |
| CAN Data Rate | Up to 2 Mbit/s in CAN FD fast phase - meets ISO 11898-2:201x loop delay symmetry requirements |
| LIN Channels | Dual LIN 2.x transceivers - integrated slave termination, SAE J2602 compliant, downward compatible with LIN 1.3 |
| Battery Monitoring | Two-channel 10-bit ADC - measures BAT/BATSENSE with ±300 mV accuracy at 20 V full scale |
| HVIO Count | 4 pins - individually configurable as HS/LS drivers or wake-up inputs with open-load diagnostics |
| Operating Modes | Normal, Standby (V1 on), Sleep (V1 off), Off, Overload, Reset, FSP - controlled via SPI and hardware events |
Pinout & Package
UJA1132AHW/5F0/0Y uses the HTQFP48 package (10 mm × 10 mm, 1.0 mm height, exposed die pad connected to GND) with thermal-enhanced construction for automotive under-hood applications.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| BAT | Battery supply input | Main power source for LIN transceivers and A/D converter channel 0; withstands ISO 7637-3 transients |
| V1 | Main regulator output | 5 V ±2 %, 500 mA supply for microcontroller; shuts off in Sleep mode; includes clamp to limit reverse current |
| TXDC / RXDC | CAN data interface | Differential transmit/receive pins for HS-CAN; support CAN FD up to 2 Mbit/s with internal biasing |
| LIN1 / LIN2 | LIN bus interfaces | Dual independent LIN physical layers compliant with SAE J2602; include integrated slave termination |
| HVIO1–HVIO4 | High-voltage I/Os | Configurable as HS/LS drivers (RON < 24 Ω) or wake-up inputs with ratiometric threshold and ground-offset tolerance |
| LIMP | Limp-home output | Fail-safe signal generator - supports static, 100 Hz/10 %, or 1.25 Hz/50 % duty cycle outputs per configuration |
| SCK / SDO / SDI / SCSN | SPI interface | 16-/24-/32-bit serial peripheral interface for register access, configuration, and diagnostics |
| RSTN | Bidirectional reset | Active-low reset I/O referenced to V1; programmable pulse length for MCU compatibility |
Key Features
| Feature | Design Value |
|---|---|
| Buck-boost SMPS | Single-coil architecture enables 2 V battery operation without external FETs or diodes - reduces BOM count and board area |
| CAN FD partial networking | ISO 11898-6:2013 compliant selective wake-up - ignores CAN FD traffic in Sleep mode to prevent false wake-ups |
| Dual LIN transceivers | Integrated LIN 2.x PHY with optimized curve shaping - improves EMC emission performance and eliminates external termination resistors |
| Non-volatile configuration | Stores power-on behavior, limp-home settings, and wake-up thresholds - enables application-specific adaptation without firmware update |
| Four HVIOs with diagnostics | Supports cyclic contact monitoring, PWM dimming (up to 250 Hz), and open-load/short-circuit detection - replaces discrete driver ICs |
Applications
| Engine Control Unit (ECU) | Body Control Module (BCM) |
|---|---|
Use Scenario: Real-time engine management under wide battery voltage range (6–16 V), including cold-crank conditions down to 2 V. IC Role / Device Role / Timing Role: Primary system basis chip supplying MCU, managing CAN/LIN comms, monitoring battery health, and executing limp-home on fault. Use Value: Maintains ECU operation during cranking dips via boost mode; dual LIN supports sensor clusters; HVIOs drive solenoids and report faults. | Use Scenario: Centralized vehicle body electronics controlling lighting, door locks, and HVAC via mixed CAN/LIN networks. IC Role / Device Role / Timing Role: Power manager and communication hub - regulates 5 V MCU rail, interfaces with CAN backbone and LIN-peripheral subnets. Use Value: Dual LIN transceivers reduce component count vs. discrete solutions; V2 regulator supplies sensors with short-to-battery protection. |
| Advanced Driver Assistance Systems (ADAS) | Electric Power Steering (EPS) |
Use Scenario: Safety-critical ADAS domain controller requiring fail-safe power sequencing, watchdog supervision, and robust CAN FD communication. IC Role / Device Role / Timing Role: Fault-tolerant SBC providing monitored 5 V supply, CAN FD up to 2 Mbit/s, and diagnostic-ready HVIOs for actuator enable signals. Use Value: Limp-home outputs activate safe-degradation modes; overtemperature shutdown prevents thermal runaway; SPI enables runtime diagnostics. | Use Scenario: High-reliability EPS module needing continuous operation during battery transients and precise torque command delivery. IC Role / Device Role / Timing Role: Integrated power + comm SBC delivering stable MCU supply, CAN interface, and protected HVIOs for motor gate drivers and fault reporting. Use Value: Boost mode sustains operation during load-dump recovery; CAN FD ensures low-latency torque commands; HVIO diagnostics detect open-circuit failures. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar System Basis Chip applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| UJA1132HW/5V0 | Same buck/boost SMPS, 5 V/500 mA V1, dual LIN, 4 HVIOs - but lacks CAN FD passive partial networking | Used where full CAN FD traffic handling is required only in Normal mode, not during Sleep | Select UJA1132HW/5V0 if partial networking and CAN FD-passive wake-up are unnecessary |
| UJA1132HW/FD/5V/4 | Identical functionality plus CAN FD partial networking and 8 HVIOs - requires additional PCB routing for extra HVIOs | Required when full CAN FD network participation during Sleep is needed, or when >4 HVIOs are used for actuation | Choose UJA1132HW/FD/5V/4 only if CAN FD-passive wake-up or expanded HVIO count is mandatory |
Compared with UJA1132HW/5V0, UJA1132AHW/5F0/0Y adds CAN FD-passive partial networking for reliable low-power wake-up in mixed CAN/CAN FD networks; versus UJA1132HW/FD/5V/4, it trades 4 fewer HVIOs for identical core SBC functionality in space-constrained layouts.
Availability
UJA1132AHW/5F0/0Y is available at Aetrix Electronics and suitable for automotive engine control, body electronics, and ADAS domain controllers requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for UJA1132AHW/5F0/0Y includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader focused on secure connectivity solutions for automotive, industrial, and IoT applications, with deep expertise in automotive-grade power management and communication ICs.
The UJA113x product line delivers integrated System Basis Chips for next-generation automotive ECUs - designed to consolidate power regulation, CAN/LIN physical layer, diagnostics, and fail-safe control into a single HTQFP48 package.
FAQ
What is the minimum battery voltage supported by UJA1132AHW/5F0/0Y during cranking?
UJA1132AHW/5F0/0Y supports operation down to 2 V battery input via its integrated buck-boost SMPS in Boost mode. This enables uninterrupted microcontroller supply during cold-crank events. The actual minimum sustainable voltage depends on output load conditions but is validated to 2 V per NXP's characterization data in the UJA113X_SERIES datasheet Rev. 2.
Does UJA1132AHW/5F0/0Y support CAN FD communication in Sleep mode?
Yes, UJA1132AHW/5F0/0Y supports CAN FD-passive partial networking per ISO 11898-6:2013. In Sleep mode, it ignores CAN FD traffic on the bus - preventing false wake-ups while allowing classic CAN nodes to remain active. This capability is enabled by default and configured via non-volatile memory settings.
How many LIN transceivers does UJA1132AHW/5F0/0Y integrate?
UJA1132AHW/5F0/0Y integrates two independent LIN transceivers compliant with LIN 2.x and SAE J2602 standards. Both channels include integrated slave termination and support downward compatibility with LIN 1.3. They operate from separate LIN bus pins (LIN1 and LIN2) and share no internal signal coupling.
What is the function of the LIMP pin on UJA1132AHW/5F0/0Y?
The LIMP pin on UJA1132AHW/5F0/0Y is a dedicated fail-safe output that activates during critical system faults. It can be configured via non-volatile memory to generate static high-side, 100 Hz/10 % duty cycle, or 1.25 Hz/50 % duty cycle signals - directly driving external 'limp-home' hardware such as warning lamps or reduced-function actuators without MCU intervention.
Can UJA1132AHW/5F0/0Y supply external loads beyond the microcontroller?
Yes, UJA1132AHW/5F0/0Y can supply external loads directly via its SMPS output (VSMPS) or auxiliary regulator (V2). The SMPS supports energy-efficient LED chain driving, while V2 delivers 5 V/100 mA with short-to-battery and loss-of-ground protection - suitable for sensors or off-board peripherals requiring robust supply isolation.
UJA1132AHW/5F0/0Y Specifications
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- Manufacturer:
- NXP Semiconductors
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- Bulk
- Product Status:
- Active
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UJA1132AHW/5F0/0Y FAQ
1.How can I place an order for UJA1132AHW/5F0/0Y through Aetrix?
Please submit a Request for Quotation (RFQ) for UJA1132AHW/5F0/0Y on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for UJA1132AHW/5F0/0Y reliable?
The price and inventory of UJA1132AHW/5F0/0Y are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for UJA1132AHW/5F0/0Y is usually 5 days.
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We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for UJA1132AHW/5F0/0Y transactions.
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UJA1132AHW/5F0/0Y orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your UJA1132AHW/5F0/0Y order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for UJA1132AHW/5F0/0Y?
For technical support, including UJA1132AHW/5F0/0Y datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your UJA1132AHW/5F0/0Y requirements.
6.How does Aetrix verify that UJA1132AHW/5F0/0Y is sourced from the original manufacturer or authorized distributors?
All UJA1132AHW/5F0/0Y products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that UJA1132AHW/5F0/0Y meets industry standards.
7.What is the process for return or replacement of UJA1132AHW/5F0/0Y?
All UJA1132AHW/5F0/0Y units undergo pre-shipment inspection (PSI). If there is an issue with UJA1132AHW/5F0/0Y, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The UJA1132AHW/5F0/0Y part is unused and in its original packaging.
Return procedure for UJA1132AHW/5F0/0Y:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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