NXP Semiconductors UJA1135AHW/3/0Y
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- UJA1135AHW/3/0Y
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- NXP Semiconductors
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UJA1135AHW/3/0Y.pdf
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- UJA1135AHW/3/0Y
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Product details
Overview
UJA1135AHW/3/0Y from NXP Semiconductors is a buck/boost System Basis Chip (SBC) for automotive ECUs, integrating a 5 V/500 mA LDO (V1), dual LIN transceivers, ISO 11898-2/6-compliant HS-CAN transceiver supporting up to 2 Mbit/s CAN FD data fields, and a low-current boost SMPS for microcontroller memory retention down to 2 V battery supply. It delivers fail-safe power management, limp-home outputs, and SPI-configurable non-volatile settings in a 48-pin HTQFP package.
For engineers reviewing the UJA1135AHW/3/0Y datasheet, UJA1135AHW/3/0Y pinout, UJA1135AHW/3/0Y application, or UJA1135AHW/3/0Y equivalent, this device serves as a complete power-and-communication hub for body control modules, gateway ECUs, and ADAS domain controllers requiring robust partial networking, battery dip resilience, and ASIL-B–capable diagnostics.
Technical Context
The UJA1135AHW/3/0Y implements a dual-mode switched-mode power supply (SMPS) with automatic buck/boost selection based on input voltage and load-optimized for memory retention during battery dips but not high-current microcontroller operation. Its CAN transceiver complies with ISO 11898-2:201x and ISO 11898-6:2013, enabling CAN FD-passive partial networking where classic CAN nodes remain asleep during CAN FD traffic without bus errors.
This variant includes two LIN transceivers (LIN 2.x/Sae J2602 compliant), four HVIOs configurable as wake-up inputs or limp-home drivers (HVIO2–HVIO4), and a 10-bit A/D converter for dual-channel battery monitoring. It lacks the 8-HVIO and CAN FD selective wake-up features found in /FD/4 variants, confirming its role as a cost-optimized dual-LIN SBC for non-partial-networking applications.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Input Range | 4.5 V to 40 V battery input; supports operation down to 2 V via boost mode for memory retention only. |
| V1 Regulator Output | 5 V nominal, ±2 % accuracy, 500 mA continuous; supplies microcontroller in Standby/Normal modes. |
| CAN Data Rate Support | Up to 2 Mbit/s in CAN FD data field; full ISO 11898-2:201x and ISO 11898-6:2013 compliance. |
| LIN Channels | Two independent LIN 2.x transceivers; downward compatible with LIN 1.3; integrated slave termination. |
| HVIO Count & Function | Four general-purpose HVIOs (HVIO1–HVIO4); configurable as wake-up inputs or limp-home outputs (static, 100 Hz, 1.25 Hz). |
| Package | HTQFP48 (SOT1181-2); 10 mm × 10 mm × 1.0 mm; exposed die pad thermally connected to GND. |
| Operating Temperature | −40 °C to +150 °C ambient; overtemperature warning and shutdown at Tth(act)otp. |
Pinout & Package
UJA1135AHW/3/0Y uses a 48-pin HTQFP package (SOT1181-2) with an exposed thermal pad internally tied to GND. Pin assignments follow the standard UJA113x pinout, with LIN2 pins (RXDL2/TXDL2) and HVIO5–HVIO8 marked "n.c." per datasheet Table 3, confirming their internal disconnection in this variant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| BAT | Battery supply input | Main power source for LIN transceivers and A/D converter channel 0; withstands ISO 7637-3 transients. |
| V1 | Main regulator output | 5 V/500 mA supply for microcontroller; disabled in Sleep mode; includes undervoltage reset and clamp protection. |
| RXDC / TXDC | CAN physical layer interface | Differential receive/transmit signals for HS-CAN bus; fully isolated when BAT = 0 V. |
| LIN1 / LIN2 | LIN bus interfaces | Two independent single-wire LIN buses; each supports slave node termination and SAE J2602 EMC. |
| HVIO2–HVIO4 | Limp-home outputs | HVIO2: static high-side driver; HVIO3: 100 Hz/10 % duty cycle; HVIO4: 1.25 Hz/50 % duty cycle-configurable via NVM. |
| SCSN / SCK / SDI / SDO | SPI interface | 16-/24-/32-bit SPI for configuration, status readback, and NVM programming; supports daisy-chaining. |
| LIMP | Failsafe activation signal | Open-drain output driven LOW during Overload or Forced Sleep Preparation to trigger external limp-home hardware. |
Key Features
| Feature | Design Value |
|---|---|
| Dual-mode SMPS | Single-coil buck/boost pre-regulator for V1/V2; soft-start, pass-through mode, and selectable pre-regulator voltage via SPI. |
| CAN FD-passive readiness | ISO 11898-6:2013 compliant bus biasing and floating CANH/CANL; enables sleep during CAN FD traffic without bus errors. |
| Configurable limp-home | Three dedicated HVIOs (HVIO2–HVIO4) provide static, pulsed, and low-frequency outputs for fail-safe ECU behavior. |
| Robust battery monitoring | 10-bit A/D converter with dual inputs (BAT/BATSENSE); ±300 mV accuracy at 20 V full scale; supports polarity diode compensation. |
| ASIL-B–capable diagnostics | Window/timeout watchdog, dual interrupt outputs (INTN1/INTN2), V1/V2/BAT undervoltage/overvoltage detection, and SPI failure reporting. |
Applications
| Body Control Module (BCM) | Gateway ECU |
|---|---|
Use Scenario: Centralized control of lighting, door locks, and window motors in modern vehicles. IC Role / Device Role / Timing Role: Primary power-and-communication hub supplying MCU, managing CAN/LIN traffic, and executing limp-home on fault. Use Value: Eliminates discrete regulators, transceivers, and watchdog ICs; reduces BOM count by ≥7 components while maintaining ASIL-B diagnostic coverage. |
Use Scenario: Aggregation and routing of messages between CAN FD backbone and legacy LIN subnetworks. IC Role / Device Role / Timing Role: Dual-LIN interface with HS-CAN transceiver and SMPS pre-regulation ensures deterministic latency and voltage stability across domains. Use Value: Enables seamless integration of new CAN FD sensors with existing LIN actuators without additional level-shifting or buffering circuitry. |
| ADAS Domain Controller | Electric Power Steering (EPS) |
Use Scenario: Power and communication management for camera/radar fusion units operating under wide battery voltage swings. IC Role / Device Role / Timing Role: Boost-mode SMPS maintains volatile memory integrity during cranking dips (down to 2 V), preventing firmware corruption. Use Value: Guarantees uninterrupted operation during engine start-stop cycles-critical for functional safety compliance (ISO 26262). |
Use Scenario: Safety-critical steering assist system requiring fail-operational behavior and rapid fault response. IC Role / Device Role / Timing Role: LIMP pin and configurable HVIO outputs drive mechanical fallback mechanisms upon MCU failure or overtemperature event. Use Value: Meets ASIL-C requirements via hardware-enforced limp-home activation independent of software execution path. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar System Basis Chip applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| UJA1132HW/5V0 | Same HTQFP48 package; higher-current boost SMPS (supports full MCU operation at 2 V); 5 V V1 regulator. | Preferred where sustained microcontroller operation-not just memory retention-is required during deep battery dips. | Select UJA1132HW/5V0 if system must maintain full MCU functionality below 6 V; UJA1135AHW/3/0Y suffices for memory hold-only use cases. |
| TLE9471-2ES | Infineon SBC with 3.3 V/500 mA VCC, single LIN, no boost SMPS; includes embedded voltage supervisor and enhanced CAN FD timing. | Targeted at simpler ECUs with single-bus architecture and no requirement for battery-dip memory retention. | Choose TLE9471-2ES for cost-sensitive, single-LIN applications without boost capability; UJA1135AHW/3/0Y adds dual-LIN and memory-retention boost. |
Compared with UJA1132HW/5V0, UJA1135AHW/3/0Y trades boost current capability for lower quiescent power and identical dual-LIN functionality; versus TLE9471-2ES, it provides greater bus flexibility (dual LIN + CAN FD) and hardware-based memory retention-making it optimal for mid-tier automotive gateways where feature density and dip resilience are balanced.
Availability
UJA1135AHW/3/0Y is available at Aetrix Electronics and suitable for body control modules, gateway ECUs, ADAS domain controllers, and electric power steering systems requiring stable component supply across automotive production lifecycles.
Supply support for UJA1135AHW/3/0Y includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT applications, with deep expertise in ASIL-certified power management and high-speed serial interfaces.
The UJA113x product line was designed specifically for next-generation automotive ECUs needing integrated power regulation, multi-protocol communication (CAN FD + dual LIN), and hardware-enforced fail-safe behavior-all in a thermally optimized HTQFP package.
FAQ
What is the primary function of the boost mode in UJA1135AHW/3/0Y?
The boost mode in UJA1135AHW/3/0Y is limited-current and intended solely to supply microcontroller volatile memory during battery voltage dips down to 2 V-not to power the full MCU. This prevents data loss during cranking events while minimizing quiescent current in Standby mode. The UJA1135AHW/3/0Y datasheet explicitly states its boost stage is "suitable for supplying the memory in a microcontroller to prevent information being lost," distinguishing it from higher-current variants like UJA1132HW/5V0.
Does UJA1135AHW/3/0Y support CAN FD partial networking with selective wake-up?
No, UJA1135AHW/3/0Y does not support CAN FD selective wake-up or ISO 11898-6–compliant partial networking. Its datasheet Table 1 confirms it lacks the "CAN partial networking; CAN FD passive" feature, which is exclusive to /FD/4 variants (e.g., UJA1131HW/FD/5V/4). UJA1135AHW/3/0Y implements only classic ISO 11898-2:201x HS-CAN with full bus biasing but no wake-up filtering for CAN FD traffic.
How many LIN transceivers does UJA1135AHW/3/0Y integrate, and are they independently configurable?
UJA1135AHW/3/0Y integrates two fully independent LIN 2.x transceivers (LIN1 and LIN2), both compliant with SAE J2602 and backward-compatible with LIN 1.3. Pins RXDL2/TXDL2 are internally connected and marked "n.c." in Table 3, confirming dual-channel operation. Each LIN bus has separate physical pins (LIN1/LIN2), dedicated receive/transmit buffers, and individual enable control via SPI-enabling concurrent communication on two distinct subnetworks.
What are the key differences between UJA1135AHW/3/0Y and UJA1131HW/5V0?
Both share the same HTQFP48 package and dual-LIN/CAN FD architecture, but UJA1131HW/5V0 features a 5 V V1 regulator and higher-current boost SMPS for full MCU operation at low battery voltage, whereas UJA1135AHW/3/0Y uses a 3.3 V V1 regulator and low-current boost optimized for memory retention only. UJA1135AHW/3/0Y also omits HVIO5–HVIO8 and associated PWM timers present in UJA1131HW/5V0, reducing pin count and complexity for cost-sensitive applications.
Can UJA1135AHW/3/0Y operate in Sleep mode while maintaining CAN/LIN wake-up capability?
Yes, UJA1135AHW/3/0Y supports full wake-up capability in Sleep mode-including CAN, LIN, and HVIO wake sources-with V1 regulator disabled to minimize current draw. The datasheet Section 7.1.1.4 confirms Sleep mode retains "at least one regular wake-up source enabled" and exits only on valid wake events. Wake-up source identification is reported via SPI, and the LIMP pin activates automatically during Overload mode entry, ensuring fail-safe behavior even with V1 off.
UJA1135AHW/3/0Y Specifications
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- NXP Semiconductors
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- Bulk
- Product Status:
- Active
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UJA1135AHW/3/0Y FAQ
1.How can I place an order for UJA1135AHW/3/0Y through Aetrix?
Please submit a Request for Quotation (RFQ) for UJA1135AHW/3/0Y on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for UJA1135AHW/3/0Y reliable?
The price and inventory of UJA1135AHW/3/0Y are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for UJA1135AHW/3/0Y is usually 5 days.
3.What payment methods are accepted for UJA1135AHW/3/0Y?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for UJA1135AHW/3/0Y transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for UJA1135AHW/3/0Y?
UJA1135AHW/3/0Y orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your UJA1135AHW/3/0Y order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for UJA1135AHW/3/0Y?
For technical support, including UJA1135AHW/3/0Y datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your UJA1135AHW/3/0Y requirements.
6.How does Aetrix verify that UJA1135AHW/3/0Y is sourced from the original manufacturer or authorized distributors?
All UJA1135AHW/3/0Y products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that UJA1135AHW/3/0Y meets industry standards.
7.What is the process for return or replacement of UJA1135AHW/3/0Y?
All UJA1135AHW/3/0Y units undergo pre-shipment inspection (PSI). If there is an issue with UJA1135AHW/3/0Y, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The UJA1135AHW/3/0Y part is unused and in its original packaging.
Return procedure for UJA1135AHW/3/0Y:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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