NXP Semiconductors UJA1169ATKZ
- Part No.:
- UJA1169ATKZ
- Manufacturer:
- NXP Semiconductors
- Category:
- Specialized
- Package:
- 20-VFDFN Exposed Pad
- Datasheet:
-
UJA1169ATKZ.pdf
- Description:
- IC MINI-CAN SYSTEM BASIS CHIP
- Quantity:
- Payment:

- Shipping:

Inventory:11,100
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Product details
Overview
UJA1169ATKZ from NXP Semiconductors is a mini high-speed CAN System Basis Chip (SBC) integrating an ISO 11898-2:2016/SAE J2284-1–5 compliant HS-CAN transceiver supporting CAN FD up to 5 Mbit/s, a scalable 5 V/3.3 V 250 mA microcontroller supply (V1), SPI interface, watchdog, and LIMP fault signaling. It operates in Standby/Sleep modes with bus and local wake-up, and supports partial networking with CAN FD-passive for automotive ECUs.
For engineers reviewing the UJA1169ATKZ datasheet, UJA1169ATKZ pinout, UJA1169ATKZ application, or UJA1169ATKZ equivalent, key selection considerations include its HVSON20 package, dual-supply capability (V1 + V2), ISO 11898-2:2016 compliance, thermal management via external PNP, and configurable non-volatile settings for power-on behavior and limp-home activation.
Technical Context
The UJA1169ATKZ implements a fully autonomous ISO 11898-2:2016-compliant CAN physical layer with floating bus pins when BAT is off, enabling reliable CAN FD fast-phase communication at up to 5 Mbit/s. Its transceiver is powered internally from V1 (in /X variants) or V2 (in non-/X variants), and features selective wake-up frame detection with CAN FD-passive support - allowing classic CAN controllers to remain in Sleep mode during CAN FD traffic without bus errors.
Power management includes three distinct operating modes: Normal (full functionality), Standby (V1 active, transceiver offline), and Sleep (V1 off, ultra-low quiescent current). Wake-up sources include standard CAN patterns, ISO-compliant selective frames (/F variants), and the WAKE pin, with wake-up source recognition and RXD-driven status signaling.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CAN Data Rate | Up to 5 Mbit/s CAN FD active; supports 50–1000 kbit/s selective wake-up bit rates |
| V1 Regulator Output | 5 V or 3.3 V ±2 %, 250 mA; switched off in Sleep mode; supports RAM retention down to 2 V battery (5 V variants) |
| V2 Regulator Output | 5 V ±2 %, 100 mA; supplies internal CAN transceiver and on-board loads; SPI-controllable on/off |
| ESD Protection | ±8 kV HBM on CAN pins; ±6 kV IEC TS 62228 on BAT, WAKE, VEXT, CAN pins |
| Bus Fault Tolerance | CANH/CANL short-circuit proof to ±58 V; protected against ISO 7637-3 automotive transients |
| Watchdog Modes | Window (Normal mode only), Timeout (Standby/Sleep), Autonomous; period selectable from 8 ms to 4 s |
| Package | HVSON20 (3.5 mm × 5.5 mm × 0.85 mm); leadless, halogen-free, RoHS-compliant |
Pinout & Package
HVSON20 package: 3.5 mm × 5.5 mm body, 0.85 mm height, exposed die pad for thermal/electrical grounding. Requires GND connection of exposed pad per datasheet recommendation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| GND (Pins 1, 4, 16, 19) | Ground reference | Four dedicated ground terminals ensure low-impedance return paths for analog, digital, and power domains |
| V1 (Pin 5) | Microcontroller supply output | Scalable 5 V/3.3 V regulator output; powers MCU and/or peripherals; disabled in Sleep mode |
| V2 (Pin 13) | On-board CAN supply | 5 V regulator exclusively for internal CAN transceiver and optional on-board hardware; SPI-controllable |
| BAT (Pin 14) | Battery input | Main power input (4.5–27 V); powers all internal circuitry except VEXT; protected per ISO 7637-3 |
| CANH / CANL (Pins 18/17) | CAN bus differential pair | ISO 11898-2:2016-compliant high-speed CAN interface; floating when BAT = 0 V |
| RXD / TXD (Pins 7/2) | CAN logic interface | RXD reflects bus state and wake-up events; TXD accepts MCU transmit data; both TTL-compatible |
| SPI (Pins 3, 9, 10, 20) | Serial Peripheral Interface | 16-/24-/32-bit SPI for configuration, diagnostics, and mode control; SCSN active-low chip select |
| LIMP (Pin 11) | Fault signaling output | Open-drain, active-low signal triggered by watchdog failure, RSTN clamping, or overtemperature |
| WAKE (Pin 12) | Local wake-up input | Active-high input enabling wake-up from Standby/Sleep; debounced and monitored independently |
| RSTN (Pin 8) | Bidirectional reset | Active-low reset pin with programmable power-on reset length; supports multiple MCU timing requirements |
Key Features
| Feature | Design Value |
|---|---|
| CAN FD-passive partial networking | Enables Sleep-mode retention during CAN FD bus activity without generating errors - critical for mixed CAN FD/classic CAN networks |
| Autonomous bus biasing | Eliminates need for external termination resistors or biasing circuits; meets ISO 11898-2:2016 common-mode voltage requirements |
| Configurable non-volatile memory | Stores power-on behavior, limp-home thresholds, reset timing, and Sleep control (SLPC bit), enabling application-specific factory programming |
| Thermal-scalable V1 regulator | Uses external PNP transistor (via VEXCC/VEXCTRL pins) to shift heat dissipation off-die, enabling stable 250 mA output under high ambient conditions |
| Dedicated LIMP output | Hardware-level fault signaling independent of MCU operation - enables fail-safe system responses during watchdog timeout or overtemperature events |
Applications
| Body Control Module (BCM) | Advanced Driver Assistance Systems (ADAS) Sensor Hub |
|---|---|
Use Scenario: Centralized power and communication management for door modules, lighting, and window controls in modern vehicles. IC Role / Device Role / Timing Role: UJA1169ATKZ serves as the primary SBC, providing regulated 5 V supply to the BCM MCU, CAN FD communication up to 5 Mbit/s, and robust wake-up handling for low-power sleep states. Use Value: Enables <10 µA Sleep current while maintaining full CAN bus monitoring, reducing parasitic drain and extending vehicle battery life between engine starts. | Use Scenario: Aggregation and conditioning of radar, camera, and ultrasonic sensor data before transmission to central ADAS ECU via high-speed CAN FD. IC Role / Device Role / Timing Role: UJA1169ATKZ acts as the sensor-side SBC, supplying 5 V to sensors via V2, isolating CAN bus faults, and enabling selective wake-up to minimize latency during object detection events. Use Value: Delivers ±58 V bus fault tolerance and ISO 7637-3 transient protection - ensuring uninterrupted sensor operation in harsh automotive environments. |
| Electric Power Steering (EPS) ECU | Automotive Gateway Module |
Use Scenario: Safety-critical steering assist system requiring deterministic communication, fault signaling, and fail-operational power sequencing. IC Role / Device Role / Timing Role: UJA1169ATKZ provides the EPS MCU's 5 V supply (V1), monitors CAN bus health, triggers LIMP output on watchdog or overtemperature fault, and maintains CAN connectivity during micro-sleep cycles. Use Value: Integrates autonomous watchdog with Window/Timeout modes and configurable reset timing - meeting ASIL-B functional safety requirements without external supervision. | Use Scenario: Interfacing between high-speed CAN FD backbone and legacy CAN subnets in multi-domain vehicle architectures. IC Role / Device Role / Timing Role: UJA1169ATKZ functions as a gateway SBC, leveraging CAN FD-passive partial networking to allow classic CAN nodes to sleep during FD traffic bursts while remaining responsive to targeted wake-up frames. Use Value: Eliminates bus arbitration conflicts and false wake-ups in heterogeneous networks - improving overall network efficiency and reducing ECU power consumption. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar CAN SBC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TJA1145ATK | Single 5 V V1 supply (250 mA); no V2 regulator; supports CAN FD up to 2 Mbit/s; lacks CAN FD-passive | Targeted at cost-sensitive, lower-bandwidth ECUs where partial networking is not required | Select when CAN FD >2 Mbit/s and CAN FD-passive are unnecessary; footprint differs (HVSON16) |
| UJA1167TK/3 | No V2 regulator; 3.3 V V1 only; no partial networking support; smaller HVSON16 package | Suitable for compact, low-power MCUs with fixed 3.3 V supply and no secondary load requirements | Choose for space-constrained designs needing only basic CAN SBC functionality without V2 or FD-passive |
Compared with TJA1145ATK and UJA1167TK/3, the UJA1169ATKZ uniquely combines 5 Mbit/s CAN FD, integrated V2 supply, and ISO-compliant CAN FD-passive - making it the only option among the three that supports full partial networking in mixed-speed CAN topologies while delivering higher bandwidth and dual-regulator flexibility.
Availability
UJA1169ATKZ is available at Aetrix Electronics and suitable for automotive body electronics, ADAS sensor hubs, electric power steering systems, and gateway modules requiring stable component supply across production lifecycles.
Supply support for UJA1169ATKZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader focused on automotive, industrial, IoT, and communication infrastructure solutions, with deep expertise in secure connectivity and embedded processing.
The UJA1169ATKZ belongs to NXP's System Basis Chip product line, designed specifically for automotive electronic control units requiring integrated CAN communication, robust power management, functional safety features, and long-term reliability in harsh environments.
FAQ
What is the maximum CAN FD data rate supported by the UJA1169ATKZ?
The UJA1169ATKZ supports CAN FD active communication up to 5 Mbit/s in the data field, compliant with ISO 11898-2:2016. This enables high-throughput firmware updates and sensor data streaming in modern automotive ECUs. The transceiver also supports selective wake-up at lower bit rates (50–1000 kbit/s) without compromising Sleep mode integrity.
Does the UJA1169ATKZ include an integrated voltage regulator for the microcontroller?
Yes, the UJA1169ATKZ integrates a scalable low-drop voltage regulator (V1) delivering either 5 V or 3.3 V at ±2 % accuracy and up to 250 mA. It supports thermal scaling via an external PNP transistor and is automatically disabled in Sleep mode to minimize quiescent current. Undervoltage reset thresholds (60–90 % of V1) are configurable in non-volatile memory for 5 V variants.
How does the UJA1169ATKZ handle wake-up in partial networking configurations?
The UJA1169ATKZ implements ISO 11898-2:2016-compliant selective wake-up with CAN FD-passive support. In /F variants, it ignores CAN FD traffic while in Sleep/Standby mode, responding only to targeted selective wake-up frames - preventing false wake-ups and enabling coexistence of CAN FD and classic CAN nodes on the same bus without protocol conflicts.
What protection features does the UJA1169ATKZ provide for automotive battery and CAN bus connections?
The UJA1169ATKZ offers ±58 V short-circuit protection on CANH/CANL pins, ±8 kV HBM ESD on CAN lines, ±6 kV IEC TS 62228 ESD on BAT/WAKE/VEXT, and full ISO 7637-3 transient immunity on BAT and CAN pins. These protections ensure reliable operation during load dump, jump-start, and other real-world automotive electrical disturbances.
Is the UJA1169ATKZ pin-compatible with other members of the UJA1169A family?
Yes, all UJA1169A variants - including UJA1169ATKZ - share identical HVSON20 pinout and mechanical footprint. Differences between variants (e.g., V1 voltage, presence of V2/VEXT, partial networking support) are implemented internally and configured via non-volatile memory or SPI, enabling flexible BOM management and design reuse across vehicle platforms.
UJA1169ATKZ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- -
- Package/Case:
- 20-VFDFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Applications:
- System Basis Chip
- Interface:
- CAN, SPI
- Voltage - Supply:
- 3V ~ 28V
- Supplier Device Package:
- 20-HVSON (3.5x5.5)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
UJA1169ATKZ FAQ
1.How can I place an order for UJA1169ATKZ through Aetrix?
Please submit a Request for Quotation (RFQ) for UJA1169ATKZ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for UJA1169ATKZ reliable?
The price and inventory of UJA1169ATKZ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for UJA1169ATKZ is usually 5 days.
3.What payment methods are accepted for UJA1169ATKZ?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for UJA1169ATKZ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for UJA1169ATKZ?
UJA1169ATKZ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your UJA1169ATKZ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for UJA1169ATKZ?
For technical support, including UJA1169ATKZ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your UJA1169ATKZ requirements.
6.How does Aetrix verify that UJA1169ATKZ is sourced from the original manufacturer or authorized distributors?
All UJA1169ATKZ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that UJA1169ATKZ meets industry standards.
7.What is the process for return or replacement of UJA1169ATKZ?
All UJA1169ATKZ units undergo pre-shipment inspection (PSI). If there is an issue with UJA1169ATKZ, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The UJA1169ATKZ part is unused and in its original packaging.
Return procedure for UJA1169ATKZ:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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