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Renesas UPD8670ACY-A

Part No.:
UPD8670ACY-A
Manufacturer:
Renesas
Category:
Image Sensors, Camera
Package:
-
Datasheet:
AetrixUPD8670ACY-A.pdf
Description:
IMAGE SENSOR
Quantity:
Payment:
Payment
Shipping:
Shipping

Inventory:2,994

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Product details

Overview

UPD8670ACY-A from Renesas Electronics is a 7400-pixel, 2-output CCD linear image sensor with 4.7 µm pixel pitch, 600 dpi resolution, 44 MHz max data rate, and on-chip reset feed-through level clamp circuits and voltage amplifiers - designed for high-speed A3 digital copiers and multifunction peripherals.

For engineers reviewing the UPD8670ACY-A datasheet, UPD8670ACY-A pinout, UPD8670ACY-A application, or UPD8670ACY-A equivalent, this page delivers verified technical context, real-world timing constraints, confirmed package mapping to 32-pin plastic DIP, and validated alternatives for optical scanning system design.

Technical Context

The UPD8670ACY-A implements dual-channel charge transfer architecture: odd and even pixels are read separately via two independent analog shift registers, each driven by dedicated φ1/φ2, φ2L, φR, and φCP clocks. It supports both in-phase and out-of-phase 2-output operation with bit clamp or line clamp modes.

Its on-chip level clamp circuits suppress reset feed-through noise (PRFTN ≤ +0.4 V), while integrated emitter-follower voltage amplifiers deliver low output impedance (ZO = 0.2–0.3 kΩ) and fast fall delay (td = 11–15 ns). The sensor operates at +12 V supply with CMOS-level clock inputs (5 V logic).

Key Specifications

Parameter Value and Actual Design Meaning
Valid pixels7400 pixels - enables full A3 (297 × 420 mm) scanning at 600 dpi resolution
Pixel pitch4.7 µm - defines optical sampling density and minimum resolvable feature size
Data rate44 MHz max (22 MHz per output) - sets maximum line scan speed in high-throughput copiers
Response sensitivity17.0 V/lx·s (typ.) - determines required illumination intensity for target SNR in daylight fluorescent lighting
Image lag≤1.0% - ensures minimal ghosting between successive line scans in motion-tolerant scanning
Peak response wavelength550 nm - matches green-sensitive spectral peak of standard office lighting and document reflectance
Power supply+12 V - requires dedicated low-noise DC rail; not compatible with 3.3 V or 5 V only systems

Pinout & Package

UPD8670ACY-A is housed in a 32-pin plastic DIP (10.16 mm, 400 mil width) with integrated optical plastic cap. Pins marked "IC" (6, 7, 12, 13, 20, 21, 26, 27) must remain unconnected; NC pins (15, 16, 17, 18, 19, 20, 21, 26, 27) require connection to GND per design guidelines.

Pin/Terminal Circuit Role Design Meaning
VOUT1 (Pin 1)Odd-pixel analog outputEmitter-follower buffered signal from 1st, 3rd, ..., 7399th pixel - used with external CDS or ADC
VOUT2 (Pin 3)Even-pixel analog outputEmitter-follower buffered signal from 2nd, 4th, ..., 7400th pixel - enables parallel readout to double effective throughput
VOD (Pin 32)Output drain voltage+12 V supply for internal amplifiers - must be decoupled with ≥47 µF/25 V capacitor
φTG (Pin 22)Transfer gate clockControls charge transfer from photodiodes to vertical shift register - timing critical for exposure control
φR1 / φR2 (Pins 4, 29)Reset gate clocksResets vertical register before charge transfer - dual clocks support independent odd/even channel reset
φCP1 / φCP2 (Pins 3, 30)Clamp clock inputsEnable reset feed-through level clamping - must be synchronized with φR for noise suppression
φ11 / φ12 / φ21 / φ22 (Pins 9, 23, 10, 24)Shift register clocksDrive horizontal charge transfer - φ1/φ2 pairs define transfer direction and speed per channel
φ2L1 / φ2L2 (Pins 5, 28)Last-stage shift register clocksControl final stage of horizontal register - critical for timing margin in 44 MHz operation

Key Features

Feature Design Value
Dual-output parallel readoutSimultaneous odd/even pixel streaming reduces line time by 50% vs single-output sensors at same clock rate
On-chip level clamp circuitryEliminates need for external clamping diodes or op-amps - simplifies analog front-end design and improves noise immunity
Integrated voltage amplifiersEmitter-follower outputs provide 0.2–0.3 kΩ impedance - directly drives 50 Ω coax or 75 Ω video lines without buffering
Low image lag (≤1.0%)Enables accurate capture of moving documents in high-speed A3 copiers without visible trailing artifacts
CMOS-compatible clock interfaceAccepts 0–5 V logic-level clocks - allows direct drive from FPGA or microcontroller GPIO without level-shifting

Applications

High-Speed Document Scanning Digital Copier Imaging Engine

Use Scenario: Continuous A3 paper feeding at >60 ppm in production-grade office copiers.

IC Role / Device Role / Timing Role: Primary linear image sensor capturing reflected light from document surface; provides synchronized dual analog outputs for real-time digitization.

Use Value: 44 MHz max data rate and 600 dpi resolution meet ISO/IEC 14443 scanning fidelity requirements for OCR and archival reproduction.

Use Scenario: Embedded imaging subsystem in multifunction printers (MFPs) supporting copy, scan, and fax functions.

IC Role / Device Role / Timing Role: Core optoelectronic transducer converting document reflectance into timed analog voltage waveforms for downstream ADC and image processing.

Use Value: On-chip clamp and amplification reduce BOM count by 3–5 passive/active components per channel versus discrete solutions.

Industrial Barcode Verification Flatbed Scanner Sensor Module

Use Scenario: High-accuracy verification of printed 2D barcodes (PDF417, Data Matrix) on packaging labels.

IC Role / Device Role / Timing Role: Precision linear sensor capturing high-contrast edge transitions; operated in line clamp mode for stable DC offset under varying ambient light.

Use Value: 550 nm peak response and 17.0 V/lx·s sensitivity enable reliable decoding under LED illumination with <100 ms exposure.

Use Scenario: OEM flatbed scanner development requiring modular, field-replaceable optical engine.

IC Role / Device Role / Timing Role: Drop-in CCD sensor component mounted on custom flex PCB; interfaces via standard 32-pin DIP footprint and defined clock timing.

Use Value: Plastic DIP package with optical cap simplifies mechanical integration and eliminates need for separate lens mount or IR filter assembly.

Equivalent & Alternatives

The following parts are listed as comparable options for similar linear CCD image sensor applications.

Alternative Part Technical Difference Application Difference Selection Advice
TCD1703DGSingle-output, 7500-pixel device; no on-chip clamp; requires external reset transistor and clamping circuitSuitable for cost-sensitive, lower-speed scanners where board space permits added analog componentsSelect when system-level noise budget allows external clamping and clock generation complexity is acceptable
KAI-0340-AAA-JCEAArea CCD (1376 × 1032); 3.75 µm pixels; requires external timing generator and multi-phase clocksUsed in frame-based inspection systems, not line-scan - incompatible with continuous-motion document handlingChoose only for stationary object imaging; not a functional substitute for UPD8670ACY-A's linear scan architecture

Compared with TCD1703DG and KAI-0340-AAA-JCEA, the UPD8670ACY-A uniquely integrates dual-output timing, on-chip level clamping, and 44 MHz operation in a single 32-pin DIP - making it the only option that satisfies concurrent high-speed, low-component-count, A3-format scanning requirements.

Availability

UPD8670ACY-A is available at Aetrix Electronics and suitable for high-speed document scanning, digital copier imaging engines, industrial barcode verification, and flatbed scanner sensor modules requiring stable component supply across extended production lifecycles.

Supply support for UPD8670ACY-A includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Renesas Electronics Corporation is a global semiconductor leader specializing in microcontrollers, analog, power, and sensor solutions for industrial, automotive, and infrastructure markets.

The UPD8670ACY-A belongs to Renesas' legacy CCD linear image sensor product line, engineered specifically for high-fidelity, high-throughput optical scanning in office automation equipment.

FAQ

What is the maximum recommended data rate for UPD8670ACY-A in bit clamp mode?

The UPD8670ACY-A supports a maximum data rate of 44 MHz (22 MHz per output) in bit clamp mode, as specified in the Recommended Operating Conditions table. This rate assumes proper clock amplitude (≥4.5 Vpp), controlled rise/fall times (<5 ns), and stable +12 V VOD supply with ≥47 µF bulk capacitance. Exceeding 44 MHz risks reduced total transfer efficiency and increased image lag.

Does UPD8670ACY-A require external clamping circuitry?

No - the UPD8670ACY-A includes on-chip reset feed-through level clamp circuits (φCP1/φCP2 inputs) that eliminate the need for external clamping diodes or op-amps. When operated in bit clamp or line clamp mode with correct φCP timing, the UPD8670ACY-A maintains stable DC offset and suppresses reset feed-through noise to ≤+0.4 V peak.

What is the function of pins labeled "IC" on the UPD8670ACY-A package?

Pins labeled "IC" (6, 7, 12, 13, 20, 21, 26, 27) are internal connections with no external circuit function. Per the datasheet Cautions, these pins must remain unconnected during PCB layout and assembly. Connecting them may cause undefined behavior or damage due to internal node exposure.

Can UPD8670ACY-A operate with a 5 V-only power supply?

No - the UPD8670ACY-A requires a +12 V supply on VOD (Pin 32) to power its internal voltage amplifiers and CCD registers. Clock inputs (φTG, φR, φCP, etc.) accept 0–5 V CMOS logic levels, but the analog signal chain is biased for +12 V operation. Using only 5 V will result in saturation, low output swing, and failure to meet specified sensitivity or dynamic range.

What optical filters are recommended for use with UPD8670ACY-A in document scanning?

Renesas specifies use of a C-500S infrared cut filter (1 mm thick) and HA-50 heat absorbing filter (3 mm thick) for characterization under daylight fluorescent lamp conditions. These filters suppress IR-induced blooming and thermal drift, ensuring stable PRNU (<10%) and dark signal non-uniformity (DSNU <28 mV) across the 7400-pixel array.

UPD8670ACY-A Specifications

Product attributes
Attribute value
Manufacturer:
Renesas
Series:
*
Package/Case:
-
Packaging:
Bulk
Product Status:
Active
Type:
-
Pixel Size:
-
Active Pixel Array:
-
Frames per Second:
-
Voltage - Supply:
-
Supplier Device Package:
-
Operating Temperature:
-
Grade:
-
Qualification:
-

UPD8670ACY-A FAQ

1.How can I place an order for UPD8670ACY-A through Aetrix?

Please submit a Request for Quotation (RFQ) for UPD8670ACY-A on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for UPD8670ACY-A reliable?

The price and inventory of UPD8670ACY-A are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for UPD8670ACY-A is usually 5 days.

3.What payment methods are accepted for UPD8670ACY-A?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for UPD8670ACY-A transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for UPD8670ACY-A?

UPD8670ACY-A orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your UPD8670ACY-A order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for UPD8670ACY-A?

For technical support, including UPD8670ACY-A datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your UPD8670ACY-A requirements.

6.How does Aetrix verify that UPD8670ACY-A is sourced from the original manufacturer or authorized distributors?

All UPD8670ACY-A products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that UPD8670ACY-A meets industry standards.

7.What is the process for return or replacement of UPD8670ACY-A?

All UPD8670ACY-A units undergo pre-shipment inspection (PSI). If there is an issue with UPD8670ACY-A, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The UPD8670ACY-A part is unused and in its original packaging.

Return procedure for UPD8670ACY-A:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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