Texas Instruments USBN9603-28MX/NOPB
- Part No.:
- USBN9603-28MX/NOPB
- Manufacturer:
- Texas Instruments
- Category:
- Controllers
- Package:
- 28-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
USBN9603-28MX/NOPB.pdf
- Description:
- IC CTRLR FULL SPD FUNC 28-SOIC
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
USBN9603-28MX/NOPB from National Semiconductor is a full-speed USB 1.1 node controller IC integrating transceiver, 3.3V regulator, Serial Interface Engine (SIE), seven endpoint FIFOs (1×8-byte control + 6×64-byte data), 8-bit parallel interface, and MICROWIRE/PLUS™ serial interface. It supports bulk, interrupt, and isochronous transfers in embedded host-peripheral applications requiring low-power, bus-powered operation.
For engineers reviewing the USBN9603-28MX/NOPB datasheet, USBN9603-28MX/NOPB pinout, USBN9603-28MX/NOPB application, or USBN9603-28MX/NOPB equivalent, this device delivers verified DMA-assisted USB connectivity with programmable clock output, hardware reset support, and dual-mode CPU interface - critical for industrial USB peripherals, legacy microcontroller integration, and resource-constrained embedded designs.
Technical Context
The USBN9603-28MX/NOPB implements a complete USB 1.1-compliant Physical Layer (PHY) and Media Access Controller (MAC), including NRZI decoding, bit stuffing/unstuffing, CRC generation/checking, and clock recovery from 24 MHz oscillator input via internal PLL (×2). Its SIE handles token detection, handshake generation (ACK/NAK/STALL), and endpoint address matching without CPU intervention.
Endpoint Pipe Controller (EPC) manages seven dedicated FIFO-based pipes: one bidirectional control endpoint (EP0) and six unidirectional endpoints (three TX, three RX), each with independent status/control registers. The device supports automatic DMA (ADMA) mode for CPU-independent 64-byte packet transfers up to 16 KB per transaction, with PID toggling and NAK recovery handled in hardware.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| USB Standard | Complies with USB Specification Rev 1.0 and 1.1; full-speed only (12 Mbps). |
| Integrated Transceiver | On-die differential + single-ended receivers and transmitter; meets USB 1.1 Chapter 7 electrical requirements. |
| FIFO Depth | Control endpoint: 8 bytes; six data endpoints: 64 bytes each - enables efficient buffering for isochronous/bulk traffic. |
| Oscillator Input | 24 MHz fundamental crystal or external clock on XIN/XOUT; internal PLL generates 48 MHz for SIE operation. |
| Power Supply | 5 V or 3.3 V operation; integrated 3.3 V regulator (V3.3 pin) powers transceiver and external 1.5 kΩ pull-up. |
| Interface Modes | Three selectable modes via MODE1/MODE0: non-multiplexed parallel, multiplexed (Intel-compatible), or MICROWIRE/PLUS™ serial. |
| DMA Support | Standard DMA and Automatic DMA (ADMA) modes; ADMA transfers up to 256 × 64-byte packets (16 KB) autonomously. |
Pinout & Package
USBN9603-28MX/NOPB is housed in a 28-pin SOIC (Small Outline Integrated Circuit) package, pin-to-pin compatible with USBN9602-28M and optimized for board-level compatibility with legacy USB peripheral designs.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC | Digital power supply input | 5 V or 3.3 V supply; powers digital logic and triggers power-on reset when ramped from GND. |
| GND / AGND | Digital and analog ground | Separate ground pins reduce noise coupling between digital core and transceiver analog section. |
| V3.3 | Transceiver 3.3 V regulator output | Supplies internal transceiver and external D+ pull-up; requires 1 µF decoupling capacitor; disableable in software. |
| XIN / XOUT | 24 MHz crystal oscillator interface | Supports fundamental 24 MHz crystal (20 pF load); external clock may drive XIN only; XOUT left floating if external clock used. |
| CLKOUT | Programmable clock output | Configurable via CCONF register; defaults to 4 MHz after reset; used for system timing or peripheral sync. |
| D+ / D− | USB differential data lines | Full-speed USB physical layer I/O; D+ requires 1.5 kΩ pull-up to 3.3 V to signal high-speed node capability. |
| MODE1 / MODE0 | Interface mode selection | Hard-wired to VCC/GND to select non-multiplexed, multiplexed, or MICROWIRE interface - no runtime reconfiguration. |
| CS / RD / WR | Parallel interface control | Active-low chip select, read strobe, and write strobe - enable standard memory-mapped access to register file. |
| A0 / D0–D7 | Address/data bus | A0 selects register address space; D0–D7 carry data or address depending on MODE setting (non-mux/mux). |
| INTR / DRQ / DACK | DMA and interrupt signaling | Configurable active-high/low/open-drain INTR; DRQ asserts when DMA ready; DACK responds to DMA request. |
Key Features
| Feature | Design Value |
|---|---|
| Fully static HALT mode | Zero-clock operation with asynchronous wake-up via USB event - essential for bus-powered suspend/resume compliance. |
| Enhanced DMA engine | ADMA mode eliminates CPU overhead for large transfers; hardware handles PID toggling, NAK recovery, and packet boundaries. |
| Integrated voltage regulator | On-chip 3.3 V regulator simplifies power design; eliminates need for external LDO when operating from 5 V supply. |
| Seven endpoint architecture | Dedicated FIFOs per endpoint eliminate shared buffer contention - guarantees deterministic latency for real-time isochronous streams. |
| Flexible microcontroller interface | Three hardware-selectable modes (non-mux/mux/MICROWIRE) enable drop-in integration with 8051, Z80, PIC, or custom ASIC controllers. |
Applications
| Industrial Data Logger | Medical Sensor Hub |
|---|---|
|
Use Scenario: Standalone temperature/humidity logger with flash storage uploads data via USB to PC upon connection. IC Role / Device Role / Timing Role: USB node controller handling enumeration, descriptor exchange, and bulk IN transfers of stored sensor records. Use Value: Integrated transceiver and 3.3 V regulator reduce BOM count; HALT mode extends battery life during idle periods between uploads. |
Use Scenario: Multi-sensor patient monitor aggregates ECG, SpO₂, and respiration signals and streams them to host PC for analysis. IC Role / Device Role / Timing Role: Real-time USB isochronous endpoint manager synchronizing sensor sampling clocks to USB frame timing (1 ms intervals). Use Value: Dedicated 64-byte RX/TX FIFOs per endpoint prevent buffer overflow during burst sensor events; ADMA offloads CPU during continuous streaming. |
| Legacy Equipment Adapter | Embedded Test Fixture |
|
Use Scenario: RS-232-to-USB converter adds USB connectivity to aging lab instruments using 8051 microcontroller. IC Role / Device Role / Timing Role: Parallel-interface USB peripheral bridging UART data to USB bulk endpoints under microcontroller control. Use Value: Non-multiplexed 8-bit interface matches 8051 bus timing; pin compatibility with USBN9602-28M allows reuse of existing PCB layouts. |
Use Scenario: Automated test station reads calibration data from DUTs and logs results via USB mass storage emulation. IC Role / Device Role / Timing Role: USB function controller implementing custom class descriptors and handling control/bulk transfers for firmware updates and log retrieval. Use Value: Seven endpoint pipes support simultaneous control requests, bulk data upload, and interrupt-driven status reporting without resource conflict. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar USB node controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| USBN9604-28MX/NOPB | Identical functionality and pinout; differs only in reset mechanism for clock generation circuit - USBN9604 uses hardware reset to stall CLKOUT during DLL synchronization. | Same use cases; preferred where precise CLKOUT phase alignment after reset is required. | Select USBN9604-28MX/NOPB if DLL lock stability post-reset is critical; otherwise USBN9603-28MX/NOPB is functionally interchangeable. |
| ISP1181BD | Single-chip USB 2.0 full-speed device controller; includes 2 kB SRAM, enhanced interrupt model, and different register map - not pin-compatible. | Supports same USB classes but requires firmware rewrite and PCB redesign due to different interface timing and pin assignment. | Choose ISP1181BD only for new designs targeting USB 2.0 compliance or needing larger integrated RAM; not a drop-in replacement. |
Compared with USBN9604-28MX/NOPB, the USBN9603-28MX/NOPB offers identical feature set and layout compatibility but omits DLL synchronization on reset - simplifying clock startup at the cost of initial CLKOUT phase uncertainty. Versus ISP1181BD, it provides proven legacy integration with minimal firmware overhead but lacks USB 2.0 readiness and on-chip memory expansion.
Availability
USBN9603-28MX/NOPB is available at Aetrix Electronics and suitable for industrial data loggers, medical sensor hubs, legacy equipment adapters, embedded test fixtures, and USB peripheral bridges requiring stable component supply and long-term obsolescence management.
Supply support for USBN9603-28MX/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
National Semiconductor was a U.S.-based semiconductor company specializing in analog and mixed-signal ICs, acquired by Texas Instruments in 2011. Its legacy USB controllers remain widely deployed in industrial and medical systems.
The USBN9603-28MX/NOPB belongs to National's USB Node Controller product line, designed specifically for cost-sensitive, low-power embedded USB peripheral implementations requiring minimal external components and direct microcontroller integration.
FAQ
What USB specification versions does the USBN9603-28MX/NOPB support?
The USBN9603-28MX/NOPB supports USB Specification versions 1.0 and 1.1 exclusively - it is a full-speed (12 Mbps) node controller and does not support USB 2.0 High-Speed (480 Mbps) or later revisions. All SIE functions, including packet formatting, CRC checking, and handshake generation, conform strictly to USB 1.1 requirements as verified in the SNOS528L datasheet.
Does the USBN9603-28MX/NOPB require an external crystal, or can it use an external clock source?
The USBN9603-28MX/NOPB supports both configurations: a 24 MHz fundamental crystal connected across XIN/XOUT, or an external 24 MHz clock applied to XIN only (with XOUT left unconnected). The internal oscillator circuit and PLL are designed for 24 MHz input; deviation invalidates USB timing compliance. Component values for crystal loading (C1/C2 ≈ 15 pF) are specified in the datasheet.
How does the USBN9603-28MX/NOPB handle USB suspend and resume events in bus-powered applications?
The USBN9603-28MX/NOPB implements a fully static HALT mode that stops all internal clocks while retaining register and FIFO contents. Upon USB resume signaling, it wakes asynchronously - enabling true bus-powered suspend/resume compliance without external wake logic. The V3.3 regulator remains active during HALT, ensuring transceiver readiness for resume detection.
Is the USBN9603-28MX/NOPB pin-compatible with the earlier USBN9602-28M?
Yes - the USBN9603-28MX/NOPB is explicitly documented as pin-to-pin compatible with USBN9602-28M in the "Outstanding Features" section of the datasheet. This allows direct replacement in existing designs without PCB modification, while adding enhanced DMA support, improved 3.3 V regulator input range, and updated register features.
What are the key differences between USBN9603-28MX/NOPB and USBN9604-28MX/NOPB?
The USBN9603-28MX/NOPB and USBN9604-28MX/NOPB are functionally identical except for their reset behavior: USBN9604 stalls CLKOUT for 214 XIN cycles during hardware reset to synchronize its internal DLL, whereas USBN9603 does not implement this DLL lock step. All registers, pinouts, timing, and features match exactly - making them interchangeable unless precise CLKOUT phase control post-reset is required.
USBN9603-28MX/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Package/Case:
- 28-SOIC (0.295", 7.50mm Width)
- Programmable:
- Not Verified
- Protocol:
- USB
- Function:
- Controller
- Interface:
- Parallel
- Standards:
- USB 1.0 and 1.1
- Voltage - Supply:
- 3V ~ 5.5V
- Current - Supply:
- 30mA
- Operating Temperature:
- 0°C ~ 70°C
- Supplier Device Package:
- 28-SOIC
- Grade:
- -
- Qualification:
- -
USBN9603-28MX/NOPB FAQ
1.How can I place an order for USBN9603-28MX/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for USBN9603-28MX/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for USBN9603-28MX/NOPB reliable?
The price and inventory of USBN9603-28MX/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for USBN9603-28MX/NOPB is usually 5 days.
3.What payment methods are accepted for USBN9603-28MX/NOPB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for USBN9603-28MX/NOPB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for USBN9603-28MX/NOPB?
USBN9603-28MX/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your USBN9603-28MX/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for USBN9603-28MX/NOPB?
For technical support, including USBN9603-28MX/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your USBN9603-28MX/NOPB requirements.
6.How does Aetrix verify that USBN9603-28MX/NOPB is sourced from the original manufacturer or authorized distributors?
All USBN9603-28MX/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that USBN9603-28MX/NOPB meets industry standards.
7.What is the process for return or replacement of USBN9603-28MX/NOPB?
All USBN9603-28MX/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with USBN9603-28MX/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The USBN9603-28MX/NOPB part is unused and in its original packaging.
Return procedure for USBN9603-28MX/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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