Texas Instruments USBN9604-28M/NOPB

Overview

USBN9604-28M/NOPB from National Semiconductor is a full-speed USB 1.1 node controller IC integrating transceiver, 3.3V regulator, Serial Interface Engine (SIE), seven endpoint FIFOs (1×8-byte control + 6×64-byte data), 8-bit parallel/MICROWIRE interface, and enhanced DMA engine. It operates at 5V or 3.3V, supports 24 MHz crystal input with internal 48 MHz PLL clock generation, and targets embedded peripheral connectivity in industrial and consumer devices.

For engineers reviewing the USBN9604-28M/NOPB datasheet, USBN9604-28M/NOPB pinout, USBN9604-28M/NOPB application, or USBN9604-28M/NOPB equivalent, this page delivers verified functional identity, validated 28-pin SOIC package mapping, confirmed endpoint architecture, real-world DMA transfer behavior, and two technically documented alternative controllers for USB 1.1 peripheral node designs.

Technical Context

The USBN9604-28M/NOPB implements a complete USB 1.1-compliant physical layer (PHY) and media access controller (MAC) with integrated differential receiver, single-ended receivers with on-chip voltage reference, and transmitter with slew-rate control. Its SIE handles bit stuffing/unstuffing, CRC generation/checking, EOP detection, and clock recovery from NRZI data using a 48 MHz derived clock.

Endpoint Pipe Controller (EPC) manages seven bidirectional/unidirectional pipes: one mandatory control endpoint (EP0) and six configurable endpoints (three transmit, three receive), each with dedicated FIFOs and independent status/control registers. The device supports automatic NAK recovery for up to 16 KB of bulk/ISO data via ADMA mode without CPU intervention.

Key Specifications

Pinout & Package

USBN9604-28M/NOPB is housed in a 28-pin Small Outline Integrated Circuit (SOIC) package with 300 mil body width and standard 0.050" lead pitch. Pin assignments are fixed per National Semiconductor SNOS528L Rev 1.3 (June 2003).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar USB 1.1 peripheral node controller applications.

Compared with USBN9604-28M/NOPB, USBN9603-28M/NOPB offers identical peripheral functionality with minor clock reset timing variation, while CY7C63723-SXC shifts design responsibility to firmware and removes integrated power and DMA acceleration-making USBN9604-28M/NOPB optimal for low-software-overhead, bus-powered embedded USB nodes.

Availability

USBN9604-28M/NOPB is available at Aetrix Electronics and suitable for industrial HMI, medical diagnostic peripherals, embedded test equipment, and legacy system USB bridging requiring stable component supply and long-term lifecycle support.

Supply support for USBN9604-28M/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

National Semiconductor was a U.S.-based semiconductor company specializing in analog and interface ICs, acquired by Texas Instruments in 2011. Its legacy USB controller portfolio emphasized integration and ease of system implementation.

The USBN9604-28M/NOPB belongs to National's Universal Serial Bus Node Controller family, designed specifically to simplify USB peripheral integration in resource-constrained embedded systems without requiring external transceivers, regulators, or DMA controllers.

FAQ

What is the primary function of the USBN9604-28M/NOPB in a USB system?

The USBN9604-28M/NOPB serves as a full-speed USB 1.1 node controller, implementing the physical layer (PHY), media access controller (MAC), and endpoint management logic required for an embedded device to act as a USB peripheral. It handles USB protocol compliance-including token recognition, data packet formatting, CRC checking, and handshake generation-while offloading data movement via its integrated DMA engine. Unlike host controllers, USBN9604-28M/NOPB does not initiate transactions but responds to host requests on endpoints EP0 through EP6.

Does the USBN9604-28M/NOPB support USB 2.0 high-speed operation?

No, the USBN9604-28M/NOPB supports only USB 1.1 full-speed operation at 12 Mbps. It lacks the high-speed transceiver circuitry, chirp signaling, and 480 Mbps PHY required for USB 2.0 compliance. Its documentation, block diagram, and electrical specifications explicitly reference USB Specification versions 1.0 and 1.1 only. Systems requiring USB 2.0 must use a different controller family, as USBN9604-28M/NOPB cannot negotiate or sustain high-speed signaling.

How does the integrated 3.3V regulator in the USBN9604-28M/NOPB function?

The USBN9604-28M/NOPB includes an on-chip 3.3V linear regulator powered from VCC (5V or 3.3V), outputting to the V3.3 pin. This regulator supplies current solely to the internal USB transceiver and the external 1.5 kΩ D+ pull-up resistor. It must be decoupled with a 1 µF tantalum capacitor to ground. When operating from a 3.3V VCC supply, the regulator is disabled, and V3.3 becomes an input pin-requiring an external 3.3V source for transceiver bias. This dual-mode operation enables flexible system-level power architecture.

What are the key differences between USBN9604-28M/NOPB and USBN9603-28M/NOPB?

The USBN9604-28M/NOPB and USBN9603-28M/NOPB share identical functionality, pinout, register map, and USB behavior. Their sole documented difference lies in the reset mechanism for the internal clock generation circuit: USBN9604 incorporates a hardware-synchronized DLL reset that stalls CLKOUT for 214 XIN cycles during hardware reset to ensure phase alignment, whereas USBN9603 uses a simpler reset scheme. All other electrical, timing, and functional specifications-including DMA, endpoint FIFOs, and interface modes-are identical per SNOS528L Rev 1.3.

Can the USBN9604-28M/NOPB operate without an external crystal?

Yes, the USBN9604-28M/NOPB supports both crystal and external clock input. When using an external 24 MHz clock source, it is connected to the XIN pin while XOUT remains unconnected. The internal oscillator circuit is bypassed, and the device derives its 48 MHz PLL clock directly from the applied signal. Crystal operation requires a 24 MHz fundamental AT-cut crystal with load capacitance matched via C1/C2 (typically 15 pF each), as specified in SNOS528L Table 1 and Figure 1. Both configurations satisfy USB 1.1 timing accuracy requirements.