Texas Instruments USBN9604SLB/NOPB

Overview

USBN9604SLB/NOPB from National Semiconductor is a full-speed USB 1.1 node controller IC integrating transceiver, 3.3V regulator, Serial Interface Engine (SIE), seven endpoint FIFOs (1×8-byte control + 6×64-byte data), 8-bit parallel/MICROWIRE interface, and enhanced DMA engine. It operates at 5V or 3.3V, supports 24 MHz crystal input with internal 48 MHz PLL clock generation, and targets embedded peripheral connectivity in industrial controllers and portable USB devices.

For engineers reviewing the USBN9604SLB/NOPB datasheet, USBN9604SLB/NOPB pinout, USBN9604SLB/NOPB application, or USBN9604SLB/NOPB equivalent, key selection criteria include endpoint FIFO depth, ADMA mode support for CPU-independent bulk transfers, programmable interrupt polarity, non-multiplexed/multiplexed bus interface flexibility, and integrated 3.3V transceiver regulation.

Technical Context

The USBN9604SLB/NOPB implements a complete USB 1.1-compliant physical layer (PHY) and media access controller (MAC) within its SIE, including NRZI decoding, bit stuffing/unstuffing, CRC generation/checking, and clock recovery from 48 MHz derived from a 24 MHz oscillator. Its endpoint pipe controller (EPC) manages seven bidirectional/unidirectional pipes with dedicated FIFOs and automatic NAK/STALL response logic.

It features two distinct DMA modes: standard DMA with external controller coordination and Automatic DMA (ADMA), enabling fully CPU-independent transfer of up to 16 KB (256 × 64-byte packets) with automatic PID toggling and NAK recovery. The MICROWIRE/PLUS interface provides serial CPU connectivity when parallel bus resources are constrained.

Key Specifications

Pinout & Package

USBN9604SLB/NOPB uses a 28-pin CSP (Chip Scale Package) with 0.5 mm pitch, optimized for compact portable designs. Pin functions are validated per National Semiconductor SNOS528L Rev 1.3 (June 2003), Section 1.2.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar USB node controller applications.

Compared with USBN9603SLB/NOPB, the USBN9604SLB/NOPB adds DLL-synchronized hardware reset behavior for improved clock stability, while versus ISP1181BD it delivers integrated regulation and true CPU-independent ADMA - reducing system-level complexity and component count in space-constrained embedded USB peripherals.

Availability

USBN9604SLB/NOPB is available at Aetrix Electronics and suitable for industrial HMI, medical data loggers, and embedded test equipment requiring stable component supply, long-lifecycle support, and verified USB 1.1 compliance.

Supply support for USBN9604SLB/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

National Semiconductor was a U.S.-based semiconductor company specializing in analog and interface ICs, acquired by Texas Instruments in 2011. Its legacy USB controllers remain widely deployed in industrial and medical systems.

The USBN960x family was designed as a cost-optimized, single-chip USB 1.1 node solution for resource-constrained microcontroller-based peripherals - emphasizing integration (transceiver + regulator + SIE + DMA), low EMI, and flexible host interface options.

FAQ

What USB specification versions does the USBN9604SLB/NOPB support?

The USBN9604SLB/NOPB supports USB Specification versions 1.0 and 1.1 only - it is a full-speed (12 Mbps), not high-speed (480 Mbps), USB device controller. It does not implement USB 2.0 or later protocols. All functional blocks - including the Serial Interface Engine, transceiver, and endpoint logic - are validated against USB 1.1 compliance requirements per the official National Semiconductor datasheet SNOS528L.

Does the USBN9604SLB/NOPB require an external crystal, or can it use an external clock source?

The USBN9604SLB/NOPB supports both configurations: a 24 MHz fundamental crystal connected between XIN and XOUT, or a 24 MHz CMOS-level clock signal applied solely to XIN (with XOUT left unconnected). The internal oscillator circuit and PLL are designed exclusively for 24 MHz input; deviation invalidates USB timing compliance. The USBN9604SLB/NOPB datasheet specifies ±2500 ppm crystal tolerance and recommends 1 MΩ R1 and 15 pF C1/C2 for typical crystal layouts.

How does the Automatic DMA (ADMA) mode in the USBN9604SLB/NOPB differ from standard DMA?

Standard DMA in the USBN9604SLB/NOPB requires external controller coordination for each 64-byte packet transfer, while ADMA mode enables fully autonomous movement of up to 16 KB (256 × 64-byte packets) without CPU intervention. ADMA handles PID toggling, NAK recovery, and endpoint handshaking internally - freeing the host MCU to perform other tasks during large bulk or isochronous transfers. This behavior is confirmed in Section 4.2 of the USBN9604SLB/NOPB datasheet SNOS528L.

Can the USBN9604SLB/NOPB operate from a 3.3V supply only, without using its internal regulator?

Yes - the USBN9604SLB/NOPB supports pure 3.3V operation. In this mode, the internal 3.3V regulator is disabled, and the V3.3 pin must be driven externally with a stable 3.3V supply to power the integrated transceiver. The device's core logic (VCC) still requires 3.3V, and all I/O tolerances (including D+, D−, and parallel interface) are specified for 3.3V operation. This configuration eliminates regulator overhead and is explicitly supported per Section 2.2 of the USBN9604SLB/NOPB datasheet.

What is the purpose of the MODE1–0 pins on the USBN9604SLB/NOPB, and what happens if they are left floating?

The MODE1–0 pins configure the USBN9604SLB/NOPB's host interface: 00=non-multiplexed, 01=multiplexed, 10=MICROWIRE, 11=reserved. They must be hard-wired to VCC or GND - floating states cause undefined interface behavior and failed initialization. National Semiconductor specifies this in Section 1.2.4 of the USBN9604SLB/NOPB datasheet, noting that improper biasing prevents register access and USB enumeration. No internal pull-ups or pull-downs exist on these pins.