Texas Instruments USBN9604SLBX/NOPB
- Part No.:
- USBN9604SLBX/NOPB
- Manufacturer:
- Texas Instruments
- Category:
- Controllers
- Package:
- 28-TFQFN, CSP
- Datasheet:
-
USBN9604SLBX/NOPB.pdf
- Description:
- IC CTRLR FULL SPEED 28-LAMCSP
- Quantity:
- Payment:

- Shipping:

Inventory:4,001
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
USBN9604SLBX/NOPB from National Semiconductor is a full-speed USB 1.1 node controller IC integrating transceiver, 3.3V regulator, Serial Interface Engine (SIE), seven endpoint FIFOs (1×8-byte control + 6×64-byte data), 8-bit parallel/MICROWIRE interface, and enhanced DMA engine. It operates at 5V or 3.3V, supports 24 MHz crystal input with internal 48 MHz PLL clock generation, and targets embedded host-peripheral bridge applications in industrial controllers and legacy USB peripherals.
For engineers reviewing the USBN9604SLBX/NOPB datasheet, USBN9604SLBX/NOPB pinout, USBN9604SLBX/NOPB application, or USBN9604SLBX/NOPB equivalent, this page delivers verified technical context, exact pin functions for SLB CSP package, real-world use cases in bus-powered devices, and two validated alternative controllers with documented functional and interface differences.
Technical Context
The USBN9604SLBX/NOPB implements a complete USB 1.1-compliant physical layer (PHY) and media access controller (MAC) with integrated differential transceiver, on-chip 3.3V regulator for D+/D− termination, and clock recovery logic extracting 12 MHz from a 48 MHz internal PLL clock derived from 24 MHz crystal input. Its SIE handles bit stuffing/unstuffing, CRC generation/checking, and endpoint address detection per USB specification.
Endpoint Pipe Controller (EPC) manages seven dedicated pipes: one bidirectional control endpoint (EP0) and six unidirectional endpoints (three TX, three RX), each with independent FIFOs and status registers. The device supports automatic NAK recovery (up to 16 KB), programmable interrupt polarity, and fully static HALT mode with asynchronous wake-up-enabling low-power bus-powered operation without external reset circuitry.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| USB Compliance | Full-Speed USB 1.0/1.1 compliant; meets Chapter 7 electrical timing and signal integrity requirements. |
| Operating Voltage | 5.0 V or 3.3 V supply; internal 3.3 V regulator powers transceiver and external 1.5 kΩ D+ pull-up. |
| FIFO Capacity | Control endpoint: 8-byte bidirectional FIFO; six data endpoints: 64-byte unidirectional FIFOs each. |
| DMA Support | Automatic DMA (ADMA) mode enables CPU-independent 64-byte packet transfers; supports up to 256×64-byte blocks (16 KB). |
| Interface Modes | Three selectable modes via MODE1/MODE0 pins: non-multiplexed parallel, multiplexed (Intel-compatible), or MICROWIRE/PLUS serial. |
| Power Management | Fully static HALT mode with asynchronous wake-up from USB events; no external reset circuit required due to integrated power-on reset. |
| Crystal Input | 24 MHz fundamental AT-cut crystal (max 50 Ω ESR, 20 pF load capacitance); XIN/XOUT pins support closed-loop oscillator or external clock. |
Pinout & Package
USBN9604SLBX/NOPB is housed in a 28-pin Chip Scale Package (CSP) with 0.5 mm pitch, optimized for compact portable designs. Pin functions are electrically identical to the SOIC-28 variant but mapped to a smaller footprint.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| RESET | Hardware Reset Input | Active-low signal that resets all registers, stalls CLKOUT for 214 XIN cycles, and disables V3.3 regulator; supports RC-based power-on reset. |
| XIN / XOUT | Oscillator Interface | Connects to 24 MHz crystal; internal oscillator circuit requires external 15 pF capacitors (C1/C2) and 1 MΩ resistor (R1) per datasheet Figure 1. |
| CLKOUT | Programmable Clock Output | Configurable via CCONF register; defaults to 4 MHz after reset; stalls during DLL synchronization in USBN9604. |
| D+ / D− | USB Differential Data Lines | Integrated transceiver with differential receiver, single-ended receivers (0.8–2.0 V threshold), and current-source transmitter; D+ requires 1.5 kΩ pull-up to V3.3. |
| V3.3 | Transceiver 3.3V Supply | Output of internal regulator (when enabled) or 3.3V input (when disabled); requires 1 µF tantalum decoupling capacitor to AGND. |
| MODE1 / MODE0 | Interface Mode Select | Hard-wired to VCC/GND to select: 00=non-multiplexed parallel, 01=multiplexed (Intel), 10=MICROWIRE, 11=reserved. |
| INTR | Configurable Interrupt Output | Software-programmable as active-high push-pull, active-low push-pull, or open-drain; tri-stated during reset. |
| DRQ / DACK | DMA Control Signals | DRQ asserts when DMA transfer is ready; DACK acknowledges DMA completion; both active-low and only used when DMA is enabled. |
Key Features
| Feature | Design Value |
|---|---|
| Enhanced DMA Engine | ADMA mode eliminates CPU intervention for bulk/isochronous transfers; handles automatic PID toggling, NAK recovery, and 64-byte packet framing. |
| Integrated Transceiver + Regulator | Eliminates need for external USB PHY and 3.3V LDO; V3.3 pin supplies transceiver and D+ pull-up resistor with single 1 µF capacitor. |
| Seven Endpoint Pipes | Hardware-managed EP0 (control) plus six configurable endpoints (3 TX/3 RX) enable concurrent interrupt, bulk, and isochronous traffic without software arbitration. |
| Low-Power HALT Mode | Fully static operation with asynchronous wake-up from USB bus events (e.g., resume, reset); reduces system standby current without external wake logic. |
| Flexible Microcontroller Interface | Three hardware-selectable modes (non-mux/mux/MICROWIRE) simplify integration with 8051, PIC, ARM7, or FPGA hosts-no glue logic required. |
Applications
| Industrial USB Adapter | Legacy Peripheral Bridge |
|---|---|
|
Use Scenario: Converting RS-232/485 fieldbus devices to USB for connection to modern SCADA systems. IC Role / Device Role / Timing Role: Full-speed USB node controller handling enumeration, descriptor exchange, and bulk data forwarding between UART and USB host. Use Value: Enables drop-in replacement of aging USB-to-serial chips with integrated transceiver and 5V/3.3V dual-supply flexibility-reducing BOM count by two components. |
Use Scenario: Adding USB connectivity to legacy printers, scanners, or POS terminals lacking native USB support. IC Role / Device Role / Timing Role: USB function controller managing control transfers (SETUP/GET_DESCRIPTOR) and isochronous data streaming for real-time image capture. Use Value: 64-byte endpoint FIFOs and ADMA support sustain >1 MB/s bulk throughput while freeing host CPU for other tasks-critical for high-resolution scanning. |
| Bus-Powered Test Equipment | Embedded USB Hub Controller |
|
Use Scenario: Portable oscilloscope probes or logic analyzers drawing power directly from USB host port. IC Role / Device Role / Timing Role: Bus-powered USB node providing self-powered enumeration and low-power HALT mode with wake-on-resume capability. Use Value: Fully static HALT mode and integrated 3.3V regulator eliminate external reset supervisor and LDO-reducing standby current to <100 µA. |
Use Scenario: Low-cost 4-port USB hub for industrial HMIs where upstream bandwidth is shared among multiple sensors. IC Role / Device Role / Timing Role: USB function controller acting as composite device with multiple interfaces (HID + CDC) using separate endpoint pipes per interface. Use Value: Seven endpoint pipes allow simultaneous HID keyboard/mouse reporting and CDC ACM serial channel-no endpoint resource contention. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar USB node controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| USBN9603SLBX/NOPB | Identical functionality and pinout; differs only in reset mechanism-USBN9603 uses power-on reset only, while USBN9604 adds hardware RESET pin assertion. | USBN9603 lacks hardware reset input; unsuitable where external reset coordination or brown-out recovery is required. | Select USBN9604SLBX/NOPB when system-level reset sequencing or robust power-fail recovery is needed. |
| Cypress CY7C63101A-SXC | USB 1.1 full-speed node with integrated transceiver but no internal voltage regulator; requires external 3.3V supply and pull-up; supports only four endpoints (1×8B + 3×16B). | Limited FIFO depth and no ADMA engine-requires CPU polling for data movement; not suitable for high-throughput isochronous streams. | Choose USBN9604SLBX/NOPB over CY7C63101A-SXC when 64-byte FIFOs, ADMA, or integrated 3.3V regulation are required. |
Compared with USBN9603SLBX/NOPB, the USBN9604SLBX/NOPB adds hardware reset control for deterministic initialization, while versus CY7C63101A-SXC it delivers deeper FIFOs, autonomous DMA, and integrated power regulation-making it superior for bus-powered, high-bandwidth embedded USB peripherals.
Availability
USBN9604SLBX/NOPB is available at Aetrix Electronics and suitable for industrial USB adapters, legacy peripheral bridges, and bus-powered test equipment requiring stable component supply across extended product lifecycles.
Supply support for USBN9604SLBX/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
National Semiconductor was a U.S.-based semiconductor company specializing in analog and interface ICs before its acquisition by Texas Instruments in 2011; its legacy USB controllers remain widely deployed in industrial systems.
The USBN9604SLBX/NOPB belongs to National's USB Node Controller family, designed specifically for cost-sensitive, space-constrained embedded systems needing full-speed USB 1.1 compliance with minimal external components.
FAQ
What is the primary function of the USBN9604SLBX/NOPB in a USB system?
The USBN9604SLBX/NOPB serves as a full-speed USB 1.1 node controller, implementing the physical layer (PHY), media access controller (MAC), transceiver, and endpoint management logic. It enables microcontrollers without native USB support to act as USB devices-handling enumeration, token processing, data transfer, and error recovery autonomously. Its integrated features reduce host CPU overhead and external component count in embedded USB peripherals.
Does the USBN9604SLBX/NOPB require an external crystal, and what are the key oscillator specifications?
Yes, the USBN9604SLBX/NOPB requires a 24 MHz fundamental AT-cut crystal connected between XIN and XOUT pins. Per the datasheet, the crystal must have ≤50 Ω series resistance, ≤10 pF shunt capacitance, and 20 pF load capacitance. External 15 pF capacitors (C1/C2) and a 1 MΩ resistor (R1) are mandatory for stable oscillation. An external 24 MHz clock may substitute for the crystal, in which case XOUT must be left unconnected.
How does the USBN9604SLBX/NOPB handle power supply for the USB transceiver?
The USBN9604SLBX/NOPB integrates a 3.3V voltage regulator accessible via the V3.3 pin. When enabled, it powers the internal transceiver and the mandatory 1.5 kΩ D+ pull-up resistor-requiring only a 1 µF tantalum capacitor to AGND. In 3.3V system designs, the regulator can be disabled, and V3.3 used as an input supply. This dual-mode operation eliminates the need for an external LDO in most implementations.
What are the key differences between USBN9604SLBX/NOPB and USBN9603SLBX/NOPB?
The USBN9604SLBX/NOPB and USBN9603SLBX/NOPB share identical functionality, pinout, and electrical characteristics except for reset behavior. The USBN9604SLBX/NOPB includes a dedicated active-low RESET pin enabling hardware-initiated reset independent of power sequencing, whereas the USBN9603SLBX/NOPB relies solely on power-on reset. This makes USBN9604SLBX/NOPB preferable in systems requiring controlled reset coordination or brown-out recovery.
Can the USBN9604SLBX/NOPB operate in low-power modes, and how is wake-up managed?
Yes, the USBN9604SLBX/NOPB supports a fully static HALT mode with asynchronous wake-up triggered by USB bus events-including resume signaling, reset pulses, or remote wakeup requests. During HALT, the core logic enters zero-power state while retaining register contents; the integrated power-on reset and clock recovery circuitry ensure reliable wake-up without external supervision-ideal for bus-powered portable instruments.
USBN9604SLBX/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Package/Case:
- 28-TFQFN, CSP
- Programmable:
- Not Verified
- Protocol:
- USB
- Function:
- Controller
- Interface:
- Parallel
- Standards:
- USB 1.0 and 1.1
- Voltage - Supply:
- 3V ~ 5.5V
- Current - Supply:
- 30mA
- Operating Temperature:
- 0°C ~ 70°C
- Supplier Device Package:
- 28-CSP (5.5x4.5)
- Grade:
- -
- Qualification:
- -
USBN9604SLBX/NOPB FAQ
1.How can I place an order for USBN9604SLBX/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for USBN9604SLBX/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for USBN9604SLBX/NOPB reliable?
The price and inventory of USBN9604SLBX/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for USBN9604SLBX/NOPB is usually 5 days.
3.What payment methods are accepted for USBN9604SLBX/NOPB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for USBN9604SLBX/NOPB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for USBN9604SLBX/NOPB?
USBN9604SLBX/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your USBN9604SLBX/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for USBN9604SLBX/NOPB?
For technical support, including USBN9604SLBX/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your USBN9604SLBX/NOPB requirements.
6.How does Aetrix verify that USBN9604SLBX/NOPB is sourced from the original manufacturer or authorized distributors?
All USBN9604SLBX/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that USBN9604SLBX/NOPB meets industry standards.
7.What is the process for return or replacement of USBN9604SLBX/NOPB?
All USBN9604SLBX/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with USBN9604SLBX/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The USBN9604SLBX/NOPB part is unused and in its original packaging.
Return procedure for USBN9604SLBX/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
USBN9604SLBX/NOPB Tags

-
PTN5150AHXMP
NXP Semiconductors

-
USB3740B-AI9-TR
Microchip Technology

-
USB3740B-AI2-TR
Microchip Technology

-
USB3300-EZK-TR
Microchip Technology

-
USB3300-EZK
Microchip Technology

-
FUSB340TMX
onsemi

-
FUSB302BMPX
onsemi

-
DP83826IRHBR
Texas Instruments

-
MCP2518FDT-E/QBB
Microchip Technology

-
FUSB302MPX
onsemi

-
MCP2518FDT-E/SL
Microchip Technology

-
FT260Q-R
FTDI, Future Technology Devices International Ltd
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

