Analog Devices Inc. VDSP-TS-PCFLOAT
- Part No.:
- VDSP-TS-PCFLOAT
- Manufacturer:
- Analog Devices Inc.
- Category:
- Software, Services
- Package:
- Datasheet:
-
VDSP-TS-PCFLOAT.pdf
- Description:
- VISUAL DSP IDE TOOL TIGERSHARC
- Quantity:
- Payment:

- Shipping:

Inventory:3,468
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
VDSP-TS-PCFLOAT from Analog Devices is a floating-license software license enabling full use of VisualDSP++ 5.0 development environment for TigerSHARC® processors on Windows XP, Windows 2000, and Windows Vista. It includes the industry-leading C/C++ compiler, VDK real-time kernel, statistical profiler, background telemetry channel (BTC), and LwIP TCP/IP stack support - all validated for SHARC and TigerSHARC architectures. It targets signal-processing-intensive real-time applications in radar, medical imaging, and high-end audio systems.
For engineers reviewing the VDSP-TS-PCFLOAT datasheet, VDSP-TS-PCFLOAT application, VDSP-TS-PCFLOAT equivalent, or VDSP-TS-PCFLOAT licensing model, this page details its scope of processor support, debug capabilities, compiler features, floating-license deployment constraints, and integration with EZ-KIT Lite evaluation hardware for TigerSHARC-based development.
Technical Context
VDSP-TS-PCFLOAT is a node-locked floating license granting concurrent access to VisualDSP++ 5.0 toolchain exclusively for TigerSHARC processors - not Blackfin or SHARC. It enables full IDE functionality including cycle-accurate simulation, compiled simulation, BTC-enabled runtime inspection, and multiprocessor debugging across TigerSHARC multicore configurations.
The license activates core infrastructure: VDK RTOS kernel with MP messaging, system service library (SSL) abstraction layer, file system service (FSS) for FAT media, and LwIP TCP/IP stack porting support - all confirmed compatible with ADSP-TS201, ADSP-TS202, and ADSP-TS203 TigerSHARC devices per Analog Devices documentation.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Licensed Processor Family | TigerSHARC only - no Blackfin or SHARC support enabled under this license. |
| License Type | Floating license - supports concurrent usage across networked workstations via FlexNet license server. |
| Host OS Support | Windows XP, Windows 2000, Windows Vista - no Linux or macOS support. |
| Compiler Target | ANSI-C/C++ compiler with MISRA-C:2004 compliance and profile-guided optimization (PGO) for TigerSHARC. |
| Debug Interface | Full JTAG and BTC support - enables real-time scalar/array read/write, pipeline visualization, and statistical profiling on TigerSHARC silicon. |
| RTOS & Middleware | Includes VisualDSP++ Kernel (VDK) with MP messaging, SSL, FSS, and LwIP TCP/IP stack - all verified for TigerSHARC memory map and interrupt architecture. |
Availability
VDSP-TS-PCFLOAT is available at Aetrix Electronics and suitable for radar signal processing, medical ultrasound beamforming, high-speed data acquisition, and industrial real-time control systems requiring stable component supply and long-term toolchain continuity.
Supply support for VDSP-TS-PCFLOAT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. is a U.S.-based semiconductor company specializing in high-performance analog, mixed-signal, and digital signal processing technologies for precision, industrial, communications, and automotive markets.
VDSP-TS-PCFLOAT belongs to the CROSSCORE® Tools product line, designed specifically to accelerate development of TigerSHARC-based embedded systems through integrated compilation, debugging, simulation, and middleware infrastructure.
FAQ
What does the "FLOAT" suffix indicate in VDSP-TS-PCFLOAT?
The "FLOAT" suffix denotes a floating license model for VDSP-TS-PCFLOAT, allowing concurrent use by multiple engineers across a local network via a FlexNet license server. Unlike node-locked licenses, VDSP-TS-PCFLOAT permits dynamic allocation of seats without binding to individual machines - ideal for team-based TigerSHARC development where engineers share access to the full VisualDSP++ 5.0 toolset including compiler, debugger, simulator, and VDK kernel.
Does VDSP-TS-PCFLOAT support SHARC or Blackfin processors?
No, VDSP-TS-PCFLOAT is strictly limited to TigerSHARC processors as defined in Analog Devices' official ordering matrix. It does not activate compiler backends, device drivers, or debug probe support for SHARC or Blackfin families. Separate licenses - VDSP-SHARC-PC-FULL and VDSP-BLKFN-PC-FULL - are required for those architectures. Attempting to target non-TigerSHARC devices with VDSP-TS-PCFLOAT results in toolchain rejection during project build or download.
Can VDSP-TS-PCFLOAT be used with ADSP-TS201, ADSP-TS202, and ADSP-TS203 TigerSHARC devices?
Yes, VDSP-TS-PCFLOAT fully supports ADSP-TS201, ADSP-TS202, and ADSP-TS203 TigerSHARC processors. All documented features - including BTC runtime inspection, statistical profiling, VDK MP messaging, and LwIP TCP/IP stack integration - are validated for these devices in VisualDSP++ 5.0 release notes and application notes. Device-specific startup code wizards and memory map configuration tools are included and functional for all three variants.
Is the VisualDSP++ Kernel (VDK) included with VDSP-TS-PCFLOAT?
Yes, VDSP-TS-PCFLOAT includes the full VisualDSP++ Kernel (VDK) - a royalty-free, real-time operating system kernel optimized for TigerSHARC multicore environments. It provides preemptive scheduling, thread management, semaphores, inter-thread messaging, events, memory pools, and multiprocessor messaging. Configuration is supported via graphical wizards within the IDE, and all VDK APIs are accessible and tested for ADSP-TS201/TS202/TS203 target deployments.
Does VDSP-TS-PCFLOAT include TCP/IP or USB connectivity support for TigerSHARC?
VDSP-TS-PCFLOAT includes LwIP TCP/IP stack support for TigerSHARC - confirmed in Analog Devices' VisualDSP++ 5.0 documentation and example projects. However, USB 2.0 device connectivity is explicitly limited to Blackfin and SHARC processors per official feature matrix; TigerSHARC lacks native USB peripheral support, so USB-related libraries and drivers are not activated or functional under VDSP-TS-PCFLOAT.
VDSP-TS-PCFLOAT Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- Visual DSP++™
- Packaging:
- Box
- Product Status:
- Active
- Type:
- Integrated Development Environment (IDE)
- Applications:
- Programming
- Edition:
- -
- License Length:
- -
- License - User Details:
- Floating Node
- Operating System:
- Windows
- For Use With/Related Products:
- TigerSHARC®
- Media Delivery Type:
- -
VDSP-TS-PCFLOAT FAQ
1.How can I place an order for VDSP-TS-PCFLOAT through Aetrix?
Please submit a Request for Quotation (RFQ) for VDSP-TS-PCFLOAT on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for VDSP-TS-PCFLOAT reliable?
The price and inventory of VDSP-TS-PCFLOAT are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for VDSP-TS-PCFLOAT is usually 5 days.
3.What payment methods are accepted for VDSP-TS-PCFLOAT?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for VDSP-TS-PCFLOAT transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for VDSP-TS-PCFLOAT?
VDSP-TS-PCFLOAT orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your VDSP-TS-PCFLOAT order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for VDSP-TS-PCFLOAT?
For technical support, including VDSP-TS-PCFLOAT datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your VDSP-TS-PCFLOAT requirements.
6.How does Aetrix verify that VDSP-TS-PCFLOAT is sourced from the original manufacturer or authorized distributors?
All VDSP-TS-PCFLOAT products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that VDSP-TS-PCFLOAT meets industry standards.
7.What is the process for return or replacement of VDSP-TS-PCFLOAT?
All VDSP-TS-PCFLOAT units undergo pre-shipment inspection (PSI). If there is an issue with VDSP-TS-PCFLOAT, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The VDSP-TS-PCFLOAT part is unused and in its original packaging.
Return procedure for VDSP-TS-PCFLOAT:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
VDSP-TS-PCFLOAT Tags
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…





