My Inquiry
My Account
Winbond Electronics Corporation W25Q128BVBJG
- Part No.:
- W25Q128BVBJG
- Manufacturer:
- Winbond Electronics Corporation
- Category:
- Memory
- Package:
- 24-TBGA
- Datasheet:
-
W25Q128BVBJG.pdf
- Description:
- IC FLASH 128MBIT SPI 24TFBGA
- Quantity:
- Payment:
- Shipping:
Inventory:3,163
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
W25Q128BVBJG from Winbond is a 128M-bit (16MB) serial NOR flash memory IC supporting Standard, Dual, and Quad SPI interfaces with up to 104 MHz clock rate, 4KB uniform sector architecture, and 1µA power-down current. It enables execute-in-place (XIP) code execution, firmware storage, and parameter retention in space-constrained embedded systems.
For engineers reviewing the W25Q128BVBJG datasheet, W25Q128BVBJG pinout, W25Q128BVBJG application, or W25Q128BVBJG equivalent, key selection criteria include Quad SPI timing compliance (QE bit required), /WP and /HOLD pin behavior in standard vs. Quad mode, 4KB sector erase granularity, and JEDEC ID (EF4018) verification for boot loader compatibility.
Technical Context
The W25Q128BVBJG implements a SPI command-set architecture with three operational modes: Standard SPI (DI/DO only), Dual SPI (IO0/IO1), and Quad SPI (IO0–IO3), where /WP and /HOLD become IO2/IO3 only after setting the non-volatile Quad Enable (QE) bit in Status Register-2. Its block diagram integrates a 256-byte page buffer, SFDP register for discoverable parameters, and three 256-byte security registers with OTP locks.
It supports full instruction-level compatibility with JEDEC JESD216B SFDP v1.6, including continuous read mode with 8-clock address overhead, erase/program suspend/resume, and hardware write protection via active-low /WP pin - disabled during Quad SPI operation. The device uses internal high-voltage generators for erase/program cycles without external VPP.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 128 M-bit (16 MB), organized as 65,536 × 256-byte pages |
| Interface Support | Standard/Dual/Quad SPI with Mode 0 & 3 clock polarity; QE bit required for Quad I/O |
| Max Clock Frequency | 104 MHz (Standard/Dual), 70 MHz (Quad); yields 208 Mbps Dual, 280 Mbps Quad effective throughput |
| Erase Granularity | Uniform 4 KB sectors (4,096 total), 32 KB blocks (256), 64 KB blocks (256), and chip erase |
| Write Endurance | 100,000 program/erase cycles per sector, guaranteed 20-year data retention |
| Supply Voltage | 2.7 V to 3.6 V single supply; 4 mA active current, <1 µA power-down current |
| Operating Temperature | –40°C to +85°C industrial grade; no derating required across full range |
| Unique Identifier | 64-bit factory-programmed serial number accessible via Read Unique ID (4Bh) instruction |
Pinout & Package
W25Q128BVBJG is packaged in an 8-pad WSON 8×6 mm (Package Code E), with exposed thermal pad. Pin functions are defined per SPI mode: /CS, CLK, DI (IO0), DO (IO1), /WP (IO2), /HOLD (IO3), VCC, GND.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| /CS | Chip Select Input | Active-low enable; must transition high→low after power-up before first instruction; places DO in high-Z when deasserted |
| CLK | Serial Clock Input | Edge-triggered timing reference for all SPI operations; supports Mode 0 (CPOL=0, CPHA=0) and Mode 3 (CPOL=1, CPHA=1) |
| DI (IO0) | Data Input / Bidirectional I/O | Input for Standard/Dual SPI; becomes IO0 in Dual/Quad mode; used for instruction/address/data input on CLK rising edge |
| DO (IO1) | Data Output / Bidirectional I/O | Output for Standard SPI; becomes IO1 in Dual/Quad mode; outputs data/status on CLK falling edge |
| /WP (IO2) | Hardware Write Protect / Bidirectional I/O | Active-low hardware lock for status register; repurposed as IO2 in Quad mode when QE=1; not available during Quad operation |
| /HOLD (IO3) | Operation Pause Input / Bidirectional I/O | Active-low pause signal for Standard/Dual SPI only; repurposed as IO3 in Quad mode; invalidates during Quad I/O |
| VCC | Power Supply | 2.7–3.6 V core supply; powers internal charge pumps for erase/program; requires local 100 nF decoupling |
| GND | Ground Reference | Signal and power ground; must be low-impedance connection to minimize noise coupling into SPI timing paths |
Key Features
| Feature | Design Value |
|---|---|
| Quad SPI XIP Enablement | Fast Read Quad I/O (EBh) with ≤8-clock address overhead enables true execute-in-place from flash without RAM copy |
| Flexible Erase Architecture | 4 KB sector erase allows independent firmware partitioning (e.g., bootloader, app, config) without disturbing adjacent regions |
| Hardware + Software Protection | Combines /WP pin control with programmable BP0–BP2, TB, SEC, and SRP bits for layered, granular write lockdown |
| Security Register Isolation | Three 256-byte security registers with OTP lock bits prevent unauthorized firmware signing key or calibration data modification |
| SFDP Compliance | JESD216B-compliant SFDP register (5Ah) provides auto-configurable timing, voltage, and feature parameters for host boot ROMs |
| Erase/Program Suspend | 75h/7Ah instructions allow background firmware update to pause/resume without losing partial sector state |
Applications
| Industrial PLC Firmware Storage | Automotive ADAS Boot Memory |
|---|---|
Use Scenario: Storing firmware images and configuration tables in programmable logic controllers operating in harsh environments with wide temperature swings. IC Role / Device Role / Timing Role: Non-volatile code and parameter storage with deterministic 4KB sector erase for field-upgradable modules and secure boot validation. Use Value: 20-year data retention and –40°C to +85°C operation ensure firmware integrity over full product lifecycle without refresh cycles. |
Use Scenario: Hosting boot code and sensor calibration data for camera/radar ECUs requiring ASIL-B compatible storage with fast random access. IC Role / Device Role / Timing Role: Primary boot memory accessed via Quad SPI XIP to reduce BOM count and eliminate external RAM dependency during cold start. Use Value: 280 Mbps Quad SPI throughput enables sub-100 ms boot time; 64-bit unique ID supports secure firmware attestation per unit. |
| Medical IoT Sensor Node | Consumer Wi-Fi Router Firmware |
Use Scenario: Retaining patient calibration profiles and usage logs in battery-powered portable diagnostic devices with strict power budgets. IC Role / Device Role / Timing Role: Low-power persistent storage with <1 µA deep-sleep current and hardware /WP lock to prevent accidental overwrite during BLE wake-up events. Use Value: 4 mA active current and 100,000-cycle endurance support daily firmware patching and multi-year clinical deployment. |
Use Scenario: Storing Linux kernel, rootfs, and wireless driver binaries in compact residential gateways where PCB area is constrained. IC Role / Device Role / Timing Role: High-density serial flash replacing parallel NOR; leverages Continuous Read Mode for efficient kernel decompression and module loading. Use Value: 8-pin WSON package saves >60% board area vs. SOIC-16; SFDP register auto-negotiates optimal timing for SoC boot ROM compatibility. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial NOR flash applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MX25L12833FZNI-08G | 128 M-bit, 3V, supports DTR Quad SPI but lacks SFDP v1.6; max clock 133 MHz (DTR) | No auto-configurable timing via SFDP; requires manual host timing setup | Preferred when higher clock speed is critical and host boot ROM supports custom timing registers |
| S25FL128SAGMFI001 | 128 M-bit, 3V, Cypress (Infineon) part with 1.8/3.0 V dual supply option; includes ECC and configurable latency | Includes on-die ECC for safety-critical reads; supports variable read latency tuning | Chosen for functional safety designs requiring error correction and configurable performance/power trade-offs |
Compared with W25Q128BVBJG, MX25L12833FZNI-08G offers higher raw clock speed but lacks SFDP-based auto-configuration, while S25FL128SAGMFI001 adds ECC and dual-voltage flexibility at the cost of larger footprint and higher unit price - making W25Q128BVBJG optimal for cost-sensitive, space-constrained XIP applications needing JEDEC-standardized boot interoperability.
Availability
W25Q128BVBJG is available at Aetrix Electronics and suitable for industrial PLCs, automotive ADAS modules, medical IoT sensors, and consumer Wi-Fi routers requiring stable component supply, long-term lifecycle assurance, and consistent parametric performance across production batches.
Supply support for W25Q128BVBJG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Winbond Electronics is a Taiwan-based semiconductor company specializing in specialty memory solutions, including serial NOR/NAND flash, RAM, and mobile DRAM, with global manufacturing and quality certifications.
The W25Q series targets embedded systems requiring high-speed, low-power, and secure code storage - designed specifically for XIP-capable microcontrollers and SoCs in industrial, automotive, and networking applications.
FAQ
What is the JEDEC manufacturer and device ID for W25Q128BVBJG?
The W25Q128BVBJG returns JEDEC ID EF4018 (manufacturer ID EFh = Winbond, memory type 40h, capacity 18h = 128 M-bit) via Read JEDEC ID (9Fh) instruction. This value is factory-programmed and used by boot ROMs for automatic flash detection and initialization sequence selection.
Does W25Q128BVBJG support Quad SPI in both standard and dual voltage modes?
W25Q128BVBJG operates exclusively at 2.7–3.6 V and supports Quad SPI only when the non-volatile Quad Enable (QE) bit in Status Register-2 is set to '1'. It does not support 1.8 V operation or dual-voltage mode - unlike some competing parts such as Spansion S25FL series.
How is the /WP pin used in W25Q128BVBJG during Quad SPI operation?
In W25Q128BVBJG, the /WP pin functions as hardware write protect only in Standard and Dual SPI modes. When Quad SPI is enabled (QE=1), /WP is reassigned as IO2 and loses its protection function - software-based protection via status register bits (BP0–BP2, SRP0/SRP1) must then be used instead.
Can W25Q128BVBJG be used for execute-in-place (XIP) without external RAM?
Yes, W25Q128BVBJG supports true XIP via Fast Read Quad I/O (EBh) and Continuous Read Mode, achieving up to 280 Mbps effective throughput. Its 8-clock address overhead and deterministic timing allow direct CPU instruction fetch from flash, eliminating need for external RAM in many Cortex-M and RISC-V designs.
What package type does the 'BJG' suffix indicate for W25Q128BVBJG?
The 'BJG' suffix in W25Q128BVBJG denotes the 8-pad WSON 8×6 mm package (Package Code E) with exposed thermal pad, RoHS-compliant matte tin finish, and industrial temperature grade (–40°C to +85°C). This is distinct from 'JG' (SOIC-16) or 'BHG' (TFBGA-24) variants.
W25Q128BVBJG Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Winbond Electronics Corporation
- Series:
- SpiFlash®
- Package/Case:
- 24-TBGA
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH - NOR
- Memory Size:
- 128Mbit
- Memory Organization:
- 16M x 8
- Memory Interface:
- SPI - Quad I/O
- Clock Frequency:
- 104 MHz
- Write Cycle Time - Word, Page:
- 50µs, 3ms
- Access Time:
- -
- Voltage - Supply:
- 2.7V ~ 3.6V
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 24-TFBGA (6x8)
W25Q128BVBJG FAQ
1.How can I place an order for W25Q128BVBJG through Aetrix?
Please submit a Request for Quotation (RFQ) for W25Q128BVBJG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for W25Q128BVBJG reliable?
The price and inventory of W25Q128BVBJG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for W25Q128BVBJG is usually 5 days.
3.What payment methods are accepted for W25Q128BVBJG?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for W25Q128BVBJG transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for W25Q128BVBJG?
W25Q128BVBJG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your W25Q128BVBJG order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for W25Q128BVBJG?
For technical support, including W25Q128BVBJG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your W25Q128BVBJG requirements.
6.How does Aetrix verify that W25Q128BVBJG is sourced from the original manufacturer or authorized distributors?
All W25Q128BVBJG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that W25Q128BVBJG meets industry standards.
7.What is the process for return or replacement of W25Q128BVBJG?
All W25Q128BVBJG units undergo pre-shipment inspection (PSI). If there is an issue with W25Q128BVBJG, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The W25Q128BVBJG part is unused and in its original packaging.
Return procedure for W25Q128BVBJG:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
W25Q128BVBJG Tags
-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology
-
AT21CS01-STUM10-T
Microchip Technology
-
AT24C02C-SSHM-T
Microchip Technology
-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics
-
AT24CS02-SSHM-T
Microchip Technology
-
93LC46BT-I/OT
Microchip Technology
-
AT24C04C-SSHM-T
Microchip Technology
-
24LC01BT-I/SN
Microchip Technology
-
24AA02UIDT-I/OT
Microchip Technology
-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
