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Winbond Electronics Corporation W25Q128BVFJP TR

Name: W25Q128BVFJP TR
Brand: Winbond Electronics Corporation
SKU: W25Q128BVFJP TR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: W25Q128BVFJP TR

Manufacturer:: Winbond Electronics Corporation

Category:: Memory

Package:: 16-SOIC (0.295", 7.50mm Width)

Datasheet:: W25Q128BVFJP TR.pdf

Description:: IC FLASH 128MBIT SPI/QUAD 16SOIC

Quantity:: RFQ Add To RFQ list

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Inventory:4,232

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Product details

Overview

W25Q128BVFJP TR from Winbond is a 128M-bit (16MB) serial NOR flash memory IC supporting Standard, Dual, and Quad SPI interfaces with up to 104MHz clock rate, 4KB uniform sector erase architecture, and 2.7–3.6V single-supply operation - used for code storage, XIP execution, and firmware parameter retention in embedded microcontrollers and IoT edge devices.

For engineers reviewing the W25Q128BVFJP TR datasheet, W25Q128BVFJP TR pinout, W25Q128BVFJP TR application, or W25Q128BVFJP TR equivalent, key selection factors include Quad SPI enable (QE bit), /WP and /HOLD pin behavior in standard vs. quad mode, 4KB sector granularity, JEDEC ID compatibility, and WSON 8x6-mm package thermal and layout constraints.

Technical Context

The W25Q128BVFJP TR implements a SPI command-set architecture with three operational modes: Standard SPI (DI/DO), Dual SPI (IO0/IO1), and Quad SPI (IO0–IO3), where IO2 and IO3 are remapped from /WP and /HOLD only when the non-volatile Quad Enable (QE) bit in Status Register-2 is set. It supports continuous read mode with ≤8-clock instruction overhead for true execute-in-place (XIP) capability.

Its memory array comprises 65,536 pages of 256 bytes each, organized into 4,096 erasable 4KB sectors and 256 erasable 64KB blocks. Erase/program suspend-resume functionality enables concurrent background operations, while SFDP register (5Ah) provides discoverable timing and feature parameters for host auto-configuration.

Key Specifications

Parameter	Value and Actual Design Meaning
Memory Density	128 M-bit (16 MB) - supports full firmware images for mid-tier MCUs without external memory expansion.
Interface Support	Standard/Dual/Quad SPI - enables scalable bandwidth: 104 MHz single-line, 208 MHz dual-output, 280 MHz quad-I/O equivalent rates.
Erase Granularity	Uniform 4 KB sectors - allows fine-grained firmware update partitioning and parameter storage without over-erasing.
Supply Voltage	2.7 V to 3.6 V - compatible with 3.3 V logic domains and low-power battery-backed systems.
Active/Power-down Current	4 mA active, <1 µA power-down - reduces system standby power in always-on edge nodes.
Data Retention	20+ years - ensures long-term reliability for industrial firmware and calibration data storage.
Endurance	100,000 program/erase cycles - supports frequent OTA update logging and runtime configuration writes.

Pinout & Package

W25Q128BVFJP TR is packaged in an 8-pad WSON 8×6 mm (Package Code E), surface-mount, lead-free, RoHS-compliant package with exposed pad for thermal dissipation. Pin 1 is /CS; pins 2–3 and 5–7 are bidirectional I/Os configurable per SPI mode; pin 4 is GND; pin 6 is CLK; pin 8 is VCC.

Pin/Terminal	Circuit Role	Design Meaning
/CS (Pin 1)	Chip Select Input	Active-low enable: drives DO/IOx high-impedance when high; required low-to-high transition resets internal state after power-up.
DO (IO1) (Pin 2)	Data Output / Bidirectional I/O	Standard/Dual SPI output or Quad SPI I/O1; must be externally pulled up for reliable read initialization.
/WP (IO2) (Pin 3)	Write Protect Input / Quad I/O2	Hardware write lock for status register when QE=0; becomes IO2 in Quad SPI (QE=1); not functional during Quad mode.
GND (Pin 4)	Ground Reference	Primary return path for VCC and I/O signals; requires low-inductance connection to minimize noise on SPI lines.
DI (IO0) (Pin 5)	Data Input / Bidirectional I/O	Standard/Dual SPI input or Quad SPI I/O0; shares same physical pin as IO0 across all modes.
CLK (Pin 6)	Serial Clock Input	Edge-triggered timing reference; supports Mode 0 and Mode 3 SPI; max 104 MHz frequency defines interface bandwidth ceiling.
/HOLD (IO3) (Pin 7)	Hold Input / Quad I/O3	Pauses ongoing SPI transaction when low (standard/dual only); becomes IO3 in Quad SPI (QE=1); inactive during Quad mode.
VCC (Pin 8)	Power Supply	2.7–3.6 V supply; requires local 100 nF ceramic decoupling adjacent to pin for stable high-speed operation.

Key Features

Feature	Design Value
Quad SPI with QE bit control	Enables 280 MHz equivalent throughput via IO0–IO3; QE must be set in Status Register-2 to activate IO2/IO3 - prevents accidental mode switching.
Continuous Read Mode	Reduces instruction overhead to ≤8 clocks per 24-bit address access, enabling deterministic XIP latency critical for real-time boot and interrupt response.
4KB uniform sector architecture	Allows independent firmware image partitioning (e.g., bootloader + app + config) without cross-sector erase conflicts or wasted space.
64-bit unique serial number	Provides hardware-rooted device identity for secure provisioning, anti-cloning, and field firmware binding without external EEPROM.
SFDP register support	JEDEC JESD216-compliant register (5Ah) delivers programmable timing parameters and feature flags to host at runtime - eliminates hard-coded driver assumptions.

Applications

Industrial PLC Firmware Storage	Automotive ADAS Boot Image
Use Scenario: Storing and executing boot firmware and safety-critical control logic in programmable logic controllers operating in harsh temperature environments (-40°C to +85°C). IC Role / Device Role / Timing Role: Primary non-volatile code storage with XIP capability, delivering deterministic instruction fetch timing via Continuous Read Mode and 4KB sector updates for field patches. Use Value: Eliminates need for parallel NOR flash or external RAM shadowing, reducing BOM count and PCB area while maintaining ASIL-B-compatible update integrity.	Use Scenario: Holding boot code and sensor fusion algorithms for automotive camera/radar ECUs requiring fast cold-boot (<500 ms) and secure firmware validation. IC Role / Device Role / Timing Role: High-reliability boot memory with JEDEC ID and 64-bit UID for cryptographic signature verification and version-controlled OTA updates. Use Value: Enables verified boot chain using hardware-unique identifiers and sector-level write protection to prevent unauthorized firmware modification.
IoT Edge Node Configuration	Medical Device Calibration Data
Use Scenario: Persisting network credentials, sensor calibration offsets, and user preferences in battery-powered wireless sensors deployed in remote locations. IC Role / Device Role / Timing Role: Low-power parameter storage with <1 µA power-down current and 100K-cycle endurance for frequent rewrites during commissioning and maintenance. Use Value: Extends battery life beyond 10 years by minimizing active current and supporting atomic 256-byte page writes without full-sector erase.	Use Scenario: Storing factory-calibrated ADC gain/offset coefficients and regulatory compliance logs in portable diagnostic equipment with strict data integrity requirements. IC Role / Device Role / Timing Role: Tamper-resistant data vault using hardware /WP pin lock, status register BP bits, and OTP-locked security registers. Use Value: Meets IEC 62304 Class C software requirements by preventing accidental or malicious overwrite of calibrated values during field servicing.

Industrial PLC Firmware Storage

Automotive ADAS Boot Image

Use Scenario: Storing and executing boot firmware and safety-critical control logic in programmable logic controllers operating in harsh temperature environments (-40°C to +85°C).

IC Role / Device Role / Timing Role: Primary non-volatile code storage with XIP capability, delivering deterministic instruction fetch timing via Continuous Read Mode and 4KB sector updates for field patches.

Use Value: Eliminates need for parallel NOR flash or external RAM shadowing, reducing BOM count and PCB area while maintaining ASIL-B-compatible update integrity.

Use Scenario: Holding boot code and sensor fusion algorithms for automotive camera/radar ECUs requiring fast cold-boot (<500 ms) and secure firmware validation.

IC Role / Device Role / Timing Role: High-reliability boot memory with JEDEC ID and 64-bit UID for cryptographic signature verification and version-controlled OTA updates.

Use Value: Enables verified boot chain using hardware-unique identifiers and sector-level write protection to prevent unauthorized firmware modification.

IoT Edge Node Configuration

Medical Device Calibration Data

Use Scenario: Persisting network credentials, sensor calibration offsets, and user preferences in battery-powered wireless sensors deployed in remote locations.

IC Role / Device Role / Timing Role: Low-power parameter storage with <1 µA power-down current and 100K-cycle endurance for frequent rewrites during commissioning and maintenance.

Use Value: Extends battery life beyond 10 years by minimizing active current and supporting atomic 256-byte page writes without full-sector erase.

Use Scenario: Storing factory-calibrated ADC gain/offset coefficients and regulatory compliance logs in portable diagnostic equipment with strict data integrity requirements.

IC Role / Device Role / Timing Role: Tamper-resistant data vault using hardware /WP pin lock, status register BP bits, and OTP-locked security registers.

Use Value: Meets IEC 62304 Class C software requirements by preventing accidental or malicious overwrite of calibrated values during field servicing.

Equivalent & Alternatives

The following parts are listed as comparable options for similar serial NOR flash applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
MX25L12833FZC-10G	128 M-bit, 104 MHz max clock, SOIC-8 and WSON-8 packages; supports Quad SPI but lacks SFDP register and 64-bit UID.	No built-in SFDP simplifies driver integration but limits runtime timing adaptation; no UID complicates secure provisioning.	Choose for cost-sensitive designs where deterministic fixed-timing drivers are acceptable and device identity is managed externally.
S25FL128SAGMFV001	128 M-bit, 80 MHz max clock, supports Quad SPI and SFDP; includes 64-bit UID but uses different status register layout and lacks /HOLD pin in WSON variant.	Lower max clock reduces XIP performance; missing /HOLD limits bus-sharing flexibility in multi-peripheral SPI systems.	Choose when SFDP and UID are required but full 104 MHz bandwidth and hold functionality are not critical.

Compared with MX25L12833FZC-10G and S25FL128SAGMFV001, W25Q128BVFJP TR delivers higher Quad SPI throughput (280 MHz equiv.), integrated SFDP for adaptive timing, and dedicated /HOLD for multi-device bus arbitration - making it optimal for XIP-critical, secure, and thermally constrained embedded systems.

Availability

W25Q128BVFJP TR is available at Aetrix Electronics and suitable for industrial automation, automotive infotainment, and medical diagnostics applications requiring stable component supply, long-lifecycle support, and RoHS-compliant packaging.

Supply support for W25Q128BVFJP TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Winbond Electronics is a Taiwan-based semiconductor company specializing in specialty memory solutions including serial NOR/NAND flash, RAM, and mobile DRAM.

The W25Q series was designed specifically for embedded systems needing high-speed, low-power, and secure code and data storage - emphasizing XIP readiness, sector-level flexibility, and hardware-assisted security features.

FAQ

What is the package type and footprint of the W25Q128BVFJP TR?

The W25Q128BVFJP TR uses an 8-pad WSON 8×6 mm package (Package Code E) with exposed thermal pad. Its footprint matches JEDEC MS-012AC standards, requires solder paste stencil aperture reduction for void control, and supports reflow per IPC-J-STD-020. Pin 1 (/CS) is marked by a dot or notch; the package is lead-free and RoHS-compliant. This compact form factor enables high-density PCB layouts in space-constrained edge devices.

Does the W25Q128BVFJP TR support execute-in-place (XIP) operation?

Yes, the W25Q128BVFJP TR supports true XIP via its Continuous Read Mode, which reduces instruction overhead to as few as 8 clock cycles per 24-bit address access. When configured for Quad SPI (QE bit set), it achieves up to 280 MHz equivalent data rates - sufficient for direct CPU instruction fetch in ARM Cortex-M7/M33 and RISC-V cores. The 4KB uniform sector architecture further enables safe in-field code updates without disrupting active execution.

How does the /WP and /HOLD pin behavior change between standard and Quad SPI modes on the W25Q128BVFJP TR?

On the W25Q128BVFJP TR, /WP (Pin 3) and /HOLD (Pin 7) function as hardware write-protect and bus-hold inputs only in Standard and Dual SPI modes. When the Quad Enable (QE) bit in Status Register-2 is set, these pins become IO2 and IO3 respectively - disabling their protective functions. This mode dependency is hardware-enforced; attempting to assert /WP or /HOLD during Quad SPI has no effect and may corrupt transfers if misconfigured.

What is the role of the SFDP register in the W25Q128BVFJP TR, and how is it accessed?

The SFDP (Serial Flash Discoverable Parameters) register in the W25Q128BVFJP TR (accessed via instruction 5Ah) provides JEDEC JESD216-compliant metadata including timing parameters, erase block sizes, and feature flags. Host processors read this register at startup to auto-configure SPI timing, eliminating hardcoded delays. Unlike static datasheet values, SFDP contents reflect actual device-binned characteristics - ensuring robust operation across voltage/temperature corners without manual tuning.

Can the W25Q128BVFJP TR be used in automotive applications requiring AEC-Q100 qualification?

No, the W25Q128BVFJP TR is not AEC-Q100 qualified. It is rated for industrial temperature range (-40°C to +85°C) and intended for commercial/industrial use. For automotive applications, Winbond offers the AEC-Q100 qualified W25Q128JWxxIQ variant in the same density and package - which adds extended temperature screening, enhanced ESD robustness, and automotive-grade traceability. Designers must verify qualification status per part number; W25Q128BVFJP TR should not be deployed in safety-critical automotive systems.

W25Q128BVFJP TR Specifications

Product attributes: Attribute value

Manufacturer:: Winbond Electronics Corporation

Series:: SpiFlash®

Package/Case:: 16-SOIC (0.295", 7.50mm Width)

Packaging:: Tape & Reel (TR)

Product Status:: Obsolete

Programmable:: Not Verified

Memory Type:: Non-Volatile

Memory Format:: FLASH

Technology:: FLASH - NOR

Memory Size:: 128Mbit

Memory Organization:: 16M x 8

Memory Interface:: SPI - Quad I/O

Clock Frequency:: 104 MHz

Write Cycle Time - Word, Page:: 50µs, 3ms

Access Time:: -

Voltage - Supply:: 2.7V ~ 3.6V

Operating Temperature:: -40°C ~ 105°C (TA)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 16-SOIC

W25Q128BVFJP TR FAQ

1.How can I place an order for W25Q128BVFJP TR through Aetrix?

Please submit a Request for Quotation (RFQ) for W25Q128BVFJP TR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for W25Q128BVFJP TR reliable?

The price and inventory of W25Q128BVFJP TR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for W25Q128BVFJP TR is usually 5 days.

3.What payment methods are accepted for W25Q128BVFJP TR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for W25Q128BVFJP TR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for W25Q128BVFJP TR?

W25Q128BVFJP TR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your W25Q128BVFJP TR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for W25Q128BVFJP TR?

For technical support, including W25Q128BVFJP TR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your W25Q128BVFJP TR requirements.

6.How does Aetrix verify that W25Q128BVFJP TR is sourced from the original manufacturer or authorized distributors?

All W25Q128BVFJP TR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that W25Q128BVFJP TR meets industry standards.

7.What is the process for return or replacement of W25Q128BVFJP TR?

All W25Q128BVFJP TR units undergo pre-shipment inspection (PSI). If there is an issue with W25Q128BVFJP TR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The W25Q128BVFJP TR part is unused and in its original packaging.

Return procedure for W25Q128BVFJP TR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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