Winbond Electronics Corporation W25Q128FVAIG

Overview

W25Q128FVAIG from Winbond is a 3.3V, 128M-bit (16MB) serial NOR flash memory IC supporting Standard/Dual/Quad SPI and QPI interfaces. It features 4KB uniform sectors, 104MHz max clock rate, 50MB/s continuous read throughput, and operates from -40°C to +85°C. It serves as nonvolatile storage for code execution (XIP), firmware updates, and parameter retention in microcontroller-based embedded systems.

For engineers reviewing the W25Q128FVAIG datasheet, W25Q128FVAIG pinout, W25Q128FVAIG application, or W25Q128FVAIG equivalent, key selection criteria include Quad SPI enable (QE bit), /HOLD vs /RESET pin configuration per package, sector-level write protection granularity, and compatibility with legacy SPI controllers requiring /WP and /HOLD functionality.

Technical Context

The W25Q128FVAIG implements a flexible SPI-compatible command set with hardware- and software-controlled write protection, including volatile/non-volatile BP bits, TB/SEC/CMP flags, and SRP lock bits. Its status register architecture supports both immediate and persistent memory protection modes.

It delivers true execute-in-place (XIP) capability via Continuous Read Mode (as few as 8 clocks to address memory) and QPI mode, reducing instruction overhead versus standard SPI. Dual/Quad I/O operation requires QE=1 in Status Register-2, repurposing /WP and /HOLD pins as IO2 and IO3 - a critical design constraint for pin-constrained layouts.

Key Specifications

Pinout & Package

W25Q128FVAIG uses an 8-pin WSON 6×5-mm package (Package Code P), with exposed pad for thermal dissipation. Pin functions are shared across SPI modes: /CS selects device, CLK synchronizes transfers, DI/DO serve as bidirectional IO0/IO1 in Dual/Quad modes, /WP and /HOLD become IO2/IO3 when QE=1.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar serial NOR flash memory applications.

Compared with MX25L12833FZC-10G, W25Q128FVAIG adds factory-programmed UID and WSON packaging; compared with S25FL128SAGMFI000, it trades Octal DTR capability for broader legacy SPI compatibility and lower cost in volume production.

Availability

W25Q128FVAIG is available at Aetrix Electronics and suitable for industrial control, automotive infotainment, medical diagnostics, and IoT edge node designs requiring stable component supply, long-lifecycle support, and verified qualification data.

Supply support for W25Q128FVAIG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Winbond Electronics is a Taiwan-based semiconductor company specializing in specialty DRAM, mobile DRAM, and serial flash memory solutions for embedded and consumer applications.

The W25Q series targets high-performance, low-power embedded systems requiring reliable code storage and execution - optimized for XIP, firmware updates, and secure parameter retention in space-constrained designs.

FAQ

What is the package type and footprint of W25Q128FVAIG?

W25Q128FVAIG uses an 8-pin WSON 6×5-mm package (Package Code P) with an exposed thermal pad. It is pin-compatible with other W25Q128FV variants in the same package family, including SOIC-8 and PDIP-8, but differs in thermal performance and board area. The WSON footprint requires controlled solder reflow profile due to the exposed pad, and PCB layout must include thermal vias under the pad for optimal heat dissipation in high-duty-cycle applications involving W25Q128FVAIG.

Does W25Q128FVAIG support hardware reset, and how is it implemented?

W25Q128FVAIG does not have a dedicated /RESET pin in its WSON-8 package. Instead, the /HOLD pin (Pin 7) can be configured as /RESET via the HOLD/RST bit (bit 7 of Status Register-3) when QE=0. This function is only available in Standard/Dual SPI mode; in Quad SPI mode (QE=1), Pin 7 becomes IO3 and /RESET is disabled. For guaranteed hardware reset, Winbond offers the 16-pin SOIC variant (W25Q128FVFIG) with a dedicated /RESET pin - W25Q128FVAIG relies on software reset (66h/99h instructions) or power-cycle recovery.

How is Quad SPI mode enabled on W25Q128FVAIG, and what changes occur to pin functions?

Quad SPI mode on W25Q128FVAIG is enabled by setting the Quad Enable (QE) bit (bit 1 of Status Register-2) to '1' using instruction 31h. Once QE=1, Pins 3 (/WP) and 7 (/HOLD) are repurposed as IO2 and IO3 respectively - disabling hardware write protection and hold functionality. This change is non-volatile unless cleared. To retain /WP and /HOLD, systems must operate in Standard or Dual SPI mode (QE=0). The W25Q128FVAIG datasheet mandates verifying QE state before initialization to avoid unexpected pin behavior.

What write protection mechanisms does W25Q128FVAIG provide beyond the /WP pin?

W25Q128FVAIG provides layered write protection: hardware /WP pin (active-low, functional only when QE=0), volatile/non-volatile Block Protect (BP2–BP0), Top/Bottom (TB), Sector Protect (SEC), Complement (CMP), and Status Register Protect (SRP0/SRP1) bits. These allow granular locking of 4KB sectors up to full-array protection. Protection settings persist across power cycles when written to non-volatile bits. The W25Q128FVAIG also supports individual sector lock/unlock (36h/39h) and global lock (7Eh), enabling dynamic firmware partitioning without physical pin dependencies.

Is W25Q128FVAIG suitable for execute-in-place (XIP) applications, and what features enable this?

Yes, W25Q128FVAIG is explicitly designed for XIP operation. Key enablers include Continuous Read Mode (≤8-clock instruction overhead), QPI interface (reduced command latency), and 104MHz clock support yielding up to 416MB/s effective bandwidth in Quad I/O mode. Its 4KB uniform sectors allow atomic firmware updates without erasing unrelated code, and the 20-year data retention ensures long-term validity of executed code. Systems using W25Q128FVAIG for XIP must configure the host controller for QPI or Fast Read Quad I/O (6Bh/EBh) and ensure stable VCC during execution - W25Q128FVAIG does not require external buffering or caching.