Winbond Electronics Corporation W25Q128FVAIQ TR
- Part No.:
- W25Q128FVAIQ TR
- Manufacturer:
- Winbond Electronics Corporation
- Category:
- Memory
- Package:
- 8-DIP (0.300", 7.62mm)
- Datasheet:
-
W25Q128FVAIQ TR.pdf
- Description:
- IC FLASH 128MBIT SPI/QUAD 8DIP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
W25Q128FVAIQ TR from Winbond is a 128M-bit (16MB) serial NOR flash memory supporting Standard/Dual/Quad SPI and QPI interfaces, operating at 2.7–3.6V with 104MHz clock rate, 4KB uniform sector erase, and true execute-in-place (XIP) capability for embedded code storage and boot applications.
For engineers reviewing the W25Q128FVAIQ TR datasheet, W25Q128FVAIQ TR pinout, W25Q128FVAIQ TR application, or W25Q128FVAIQ TR equivalent, this page delivers verified package mapping (8-pin WSON 6×5-mm), confirmed Quad Enable (QE) bit behavior, JEDEC ID support, SFDP register compliance, and real-world XIP timing constraints - all critical for MCU boot loader integration and industrial firmware design.
Technical Context
The W25Q128FVAIQ TR implements a flexible SPI-compatible memory architecture with three operational modes: standard single-I/O, dual-I/O (IO0/IO1), and quad-I/O (IO0–IO3), where the /WP and /HOLD pins become IO2 and IO3 only when the non-volatile QE bit in Status Register-2 is set to 1. Its 65,536 × 256-byte pages support 1–256 byte page programming and erase granularity down to 4KB sectors.
It integrates volatile/non-volatile status register protection (SRP0/SRP1), top/bottom block protect (TB), sector lock/unlock commands (36h/39h), and hardware write-protection via active-low /WP and /HOLD pins - all configurable independently of software control. The device supports JEDEC JESD216 SFDP v1.5 for automatic parameter discovery and includes a 64-bit unique ID per unit.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 128 M-bit (16 MB), organized as 65,536 × 256-byte programmable pages |
| Interface Modes | Standard SPI, Dual I/O, Quad I/O, and QPI - requires QE=1 for quad mode; /WP and /HOLD repurposed as IO2/IO3 |
| Max Clock Frequency | 104 MHz (SPI), enabling 208 MB/s dual-I/O and 416 MB/s quad-I/O effective throughput |
| Erase Granularity | Uniform 4KB sectors (4,096 total), 32KB blocks (256), 64KB blocks (128), and full chip erase |
| Write Endurance | ≥100,000 program/erase cycles per sector, with ≥20-year data retention at +25°C |
| Supply Voltage | 2.7 V to 3.6 V; active current ≤4 mA typical, power-down current ≤1 µA typical |
| Operating Temp | –40°C to +85°C industrial grade; validated across full voltage and temperature range |
Pinout & Package
W25Q128FVAIQ TR uses the 8-pad WSON 6×5-mm package (Package Code P), with exposed thermal pad. Pin 1 is /CS; pins 2–3 are bidirectional IOs (DO/IO1, /WP/IO2); pin 4 is GND; pin 5 is DI/IO0; pin 6 is CLK; pin 7 is /HOLD or /RESET (IO3); pin 8 is VCC.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| /CS (Pin 1) | Chip Select input | Active-low enable: high = high-Z outputs and standby current; must transition high→low after power-up before first instruction |
| DO / IO1 (Pin 2) | Bidirectional data I/O | Output in standard SPI; input/output in dual/quad modes; used for read data and status register reads |
| /WP / IO2 (Pin 3) | Hardware write-protect or quad I/O | Active-low hardware lock for status register; disabled as /WP when QE=1 (becomes IO2) |
| GND (Pin 4) | Ground reference | Primary signal and power return; decoupling capacitor required between Pin 4 and Pin 8 |
| DI / IO0 (Pin 5) | Bidirectional data I/O | Input in standard SPI; input/output in dual/quad modes; carries instructions, addresses, and program data |
| CLK (Pin 6) | Serial clock input | Edge-triggered timing source: rising edge for input, falling edge for output in all SPI modes |
| /HOLD or /RESET (Pin 7) | Pause or reset control | Active-low hold function (suspends ongoing operation); functions as /RESET only when QE=0 and configured via SR |
| VCC (Pin 8) | Power supply | 2.7–3.6 V core supply; requires local 100 nF ceramic decoupling capacitor near Pin 8 |
Key Features
| Feature | Design Value |
|---|---|
| Quad Peripheral Interface (QPI) | Reduces instruction overhead to one 8-bit opcode per transaction, enabling deterministic XIP latency and eliminating mode-switching delays |
| Erase/Program Suspend & Resume | Allows background erase or program to be paused (75h) and resumed (7Ah) without data loss - essential for real-time interrupt handling |
| JEDEC JESD216 SFDP v1.5 | Enables automatic detection of memory geometry, timing parameters, and feature sets by host bootloader without hard-coded constants |
| 64-bit Unique Serial Number | Factory-programmed per unit; enables secure device binding, firmware licensing, and anti-cloning in production firmware deployment |
| Three 256-byte Security Registers | OTP-lockable storage for cryptographic keys, calibration data, or secure boot manifests - protected by LB1–LB3 bits in Status Register-3 |
| Continuous Read Mode with Wrap | Supports 8/16/32/64-byte burst wrap addressing; reduces address overhead to just 8 clocks for first access - critical for low-latency XIP execution |
Applications
| Industrial PLC Firmware Storage | Automotive Infotainment Boot Memory |
|---|---|
Use Scenario: Storing firmware images and configuration data for programmable logic controllers operating in harsh environments with wide temperature swings and EMI exposure. IC Role / Device Role / Timing Role: Primary non-volatile code storage with execute-in-place (XIP) capability, directly mapped into ARM Cortex-M4/M7 instruction bus via QPI interface. Use Value: Eliminates need for external RAM loading; 4KB sector erase enables field-upgradable modules without full reflash; -40°C to +85°C rating ensures reliability in uncontrolled cabinet environments. |
Use Scenario: Holding boot code, OS kernel, and UI assets for head-unit systems requiring fast cold-boot (<500 ms) and secure over-the-air (OTA) update rollback. IC Role / Device Role / Timing Role: Secure boot ROM replacement with SFDP auto-discovery and 64-bit UID for asymmetric key binding during UEFI Secure Boot validation. Use Value: QPI mode achieves 416 MB/s effective bandwidth for parallel instruction fetch; security registers store root-of-trust keys; OTP locks prevent tampering post-certification. |
| Medical Imaging Device Configuration | Smart Energy Meter Firmware |
Use Scenario: Retaining calibration tables, sensor compensation coefficients, and regulatory-compliant audit logs in portable ultrasound and MRI subsystems. IC Role / Device Role / Timing Role: Parameter and data log storage with hardware write-protection (/WP pin) and individual sector lock (36h command) to meet IEC 62304 Class C requirements. Use Value: 100,000+ erase cycles ensure >10 years of daily recalibration logging; top/bottom protect bits (TB) isolate boot code from user-modifiable regions. |
Use Scenario: Hosting firmware, tariff tables, and encrypted metering history in ANSI C12.22-compliant smart meters deployed in utility substations and residential endpoints. IC Role / Device Role / Timing Role: Tamper-resistant firmware repository with security registers storing AES-128 keys and SFDP-defined timing for guaranteed read stability under brown-out conditions. Use Value: Power-down current <1 µA extends battery life during grid outages; JEDEC ID and unique UID support fleet-level firmware version tracking and remote diagnostics. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial NOR flash memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MX25L12833FZC-10G | 128M-bit, 104MHz max, SOIC-8 and WSON-8 packages; supports SFDP but lacks QPI mode and security registers | No QPI or security register support; limited to standard/dual SPI; no 64-bit UID or OTP-lockable security space | Select when QPI/XIP and cryptographic key storage are not required; lower cost for basic firmware storage |
| S25FL128SAGMFV001 | 128M-bit, 133MHz max, supports Octal DTR mode; includes 256-byte OTP area and 64-bit UID; requires different SFDP parsing | Higher clock rate and octal mode available; OTP layout and security register access differ; pinout incompatible with WSON-8 | Choose for higher bandwidth needs and legacy Cypress toolchain compatibility; requires PCB redesign due to 16-pin SOIC or BGA packaging |
Compared with MX25L12833FZC-10G and S25FL128SAGMFV001, the W25Q128FVAIQ TR uniquely combines QPI-mode XIP, factory-programmed UID, and three OTP-lockable security registers in an industry-standard 8-pin WSON package - making it optimal for secure, low-latency embedded boot applications without layout change.
Availability
W25Q128FVAIQ TR is available at Aetrix Electronics and suitable for industrial PLC firmware storage, automotive infotainment boot memory, and medical imaging device configuration requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for W25Q128FVAIQ TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Winbond Electronics is a Taiwan-based semiconductor company specializing in specialty memory solutions, including SPI NOR/NAND flash, RAM, and mobile DRAM, serving industrial, automotive, and consumer markets since 1987.
The W25Q series targets embedded systems requiring high-reliability, low-power, and multi-interface serial flash - designed specifically for code shadowing, XIP execution, and secure firmware storage in resource-constrained MCUs.
FAQ
What is the package type and footprint compatibility of the W25Q128FVAIQ TR?
The W25Q128FVAIQ TR uses an 8-pad WSON 6×5-mm package (Package Code P) with exposed thermal pad. It shares pinout and footprint compatibility with other Winbond W25Q128FV variants in the same WSON-8 package, including identical /CS, DO, /WP, GND, DI, CLK, /HOLD or /RESET, and VCC assignments. No PCB redesign is needed when substituting within this package family.
Does the W25Q128FVAIQ TR support execute-in-place (XIP) operation, and what interface mode enables it?
Yes, the W25Q128FVAIQ TR supports true execute-in-place (XIP) operation using its Quad Peripheral Interface (QPI) mode, which reduces instruction overhead and enables deterministic, low-latency instruction fetch. QPI mode is enabled by setting the Quad Enable (QE) bit in Status Register-2; once activated, the device accepts 8-bit opcodes with automatic address increment and wrap support.
How is hardware write protection implemented on the W25Q128FVAIQ TR?
Hardware write protection on the W25Q128FVAIQ TR is implemented via the active-low /WP pin, which - when held low - prevents writes to the status register regardless of software commands. This protection works in conjunction with status register bits (BP2–BP0, TB, SEC) and is only active in standard/dual SPI modes; /WP becomes IO2 in quad mode when QE=1.
What unique identifiers and security features does the W25Q128FVAIQ TR provide?
The W25Q128FVAIQ TR provides a factory-programmed 64-bit unique serial number accessible via instruction 4Bh, three 256-byte security registers (with OTP lock bits LB1–LB3 in Status Register-3), and JEDEC-standard manufacturer/device ID (9Fh). These features enable secure device binding, firmware licensing, and tamper-resistant storage of cryptographic keys or calibration data.
Can the W25Q128FVAIQ TR be used in systems requiring extended temperature operation beyond commercial grade?
Yes, the W25Q128FVAIQ TR is rated for –40°C to +85°C industrial temperature operation, validated across full voltage (2.7–3.6 V) and timing specifications. Its endurance (≥100,000 cycles) and data retention (≥20 years at +25°C) are guaranteed across this range, making it suitable for outdoor, automotive, and industrial control applications without derating.
W25Q128FVAIQ TR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Winbond Electronics Corporation
- Series:
- SpiFlash®
- Package/Case:
- 8-DIP (0.300", 7.62mm)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Discontinued at Digi-Key
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH - NOR
- Memory Size:
- 128Mbit
- Memory Organization:
- 16M x 8
- Memory Interface:
- SPI - Quad I/O, QPI
- Clock Frequency:
- 104 MHz
- Write Cycle Time - Word, Page:
- 50µs, 3ms
- Access Time:
- -
- Voltage - Supply:
- 2.7V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 8-PDIP
W25Q128FVAIQ TR FAQ
1.How can I place an order for W25Q128FVAIQ TR through Aetrix?
Please submit a Request for Quotation (RFQ) for W25Q128FVAIQ TR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for W25Q128FVAIQ TR reliable?
The price and inventory of W25Q128FVAIQ TR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for W25Q128FVAIQ TR is usually 5 days.
3.What payment methods are accepted for W25Q128FVAIQ TR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for W25Q128FVAIQ TR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for W25Q128FVAIQ TR?
W25Q128FVAIQ TR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your W25Q128FVAIQ TR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for W25Q128FVAIQ TR?
For technical support, including W25Q128FVAIQ TR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your W25Q128FVAIQ TR requirements.
6.How does Aetrix verify that W25Q128FVAIQ TR is sourced from the original manufacturer or authorized distributors?
All W25Q128FVAIQ TR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that W25Q128FVAIQ TR meets industry standards.
7.What is the process for return or replacement of W25Q128FVAIQ TR?
All W25Q128FVAIQ TR units undergo pre-shipment inspection (PSI). If there is an issue with W25Q128FVAIQ TR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The W25Q128FVAIQ TR part is unused and in its original packaging.
Return procedure for W25Q128FVAIQ TR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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