Winbond Electronics Corporation W25Q128FVBIG

Overview

W25Q128FVBIG from Winbond is a 3.3V, 128M-bit (16MB) serial NOR flash memory supporting Standard/Dual/Quad SPI and QPI interfaces. It features 4KB uniform sectors, 104MHz max clock frequency, 50MB/s continuous read throughput, and operates from -40°C to +85°C. It enables XIP (execute-in-place) code execution in embedded microcontrollers and stores firmware, configuration data, and boot images.

For engineers reviewing the W25Q128FVBIG datasheet, W25Q128FVBIG pinout, W25Q128FVBIG application, or W25Q128FVBIG equivalent, key selection criteria include Quad SPI enable (QE bit), /HOLD vs /RESET pin behavior per package, sector protection granularity, JEDEC ID compatibility, and power-down current (<1µA typical).

Technical Context

The W25Q128FVBIG implements a flexible SPI-compatible command set with hardware- and software-controlled write protection. Its status register includes volatile/non-volatile BP2–BP0, TB, SEC, CMP, SRP0/SRP1, QE, and HOLD/RST bits that govern memory access modes and pin functionality.

It supports four distinct I/O protocols: Standard SPI (4-wire), Dual SPI (4-wire with bidirectional IO0/IO1), Quad SPI (6-wire with IO0–IO3), and QPI (6-wire with instruction/data multiplexing). The /WP and /HOLD pins revert to IO2 and IO3 respectively when QE=1, enabling full quad operation but disabling hardware write protect and hold functions on 8-pin packages.

Key Specifications

Pinout & Package

W25Q128FVBIG uses an 8-pin SOIC 208-mil (Package Code S) with standard SPI pinout. Pin functions are configurable: /HOLD and /WP become IO3 and IO2 respectively when Quad Enable (QE) bit is set.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar serial NOR flash applications.

Compared with MX25L12833FZC-10G and S25FL128SAGMFI001, the W25Q128FVBIG delivers higher effective throughput via QPI and standardized SFDP auto-configuration, but lacks hardware ECC and automotive qualification-making it optimal for cost-sensitive industrial and consumer designs requiring maximum SPI speed and flexibility.

Availability

W25Q128FVBIG is available at Aetrix Electronics and suitable for embedded boot storage, firmware update partitions, and secure configuration data retention requiring stable component supply, long-term lifecycle assurance, and consistent parametric performance across production batches.

Supply support for W25Q128FVBIG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Winbond Electronics is a Taiwan-based semiconductor company specializing in specialty DRAM, mobile DRAM, and serial flash memory solutions since 1987.

The W25Q series targets high-performance embedded systems requiring fast, reliable, and space-efficient code and data storage-designed specifically for MCU boot, OTA updates, and secure parameter retention in resource-constrained environments.

FAQ

What is the function of the /HOLD pin on W25Q128FVBIG, and does it remain available in Quad SPI mode?

The /HOLD pin on W25Q128FVBIG pauses ongoing SPI transfers when pulled low while /CS is active, allowing bus sharing among multiple devices. In Quad SPI mode (enabled by setting the QE bit in Status Register-2), the /HOLD pin is reassigned as IO3 and no longer functions as a hold input. This behavior is explicitly defined in the W25Q128FVBIG datasheet Section 4.4 and Figure 1a–c, and applies only to 8-pin packages like the SOIC used in W25Q128FVBIG.

Does W25Q128FVBIG support execute-in-place (XIP) operation, and what conditions must be met?

Yes, W25Q128FVBIG supports true XIP operation via its Continuous Read Mode, which minimizes instruction overhead to as few as 8 clock cycles for address setup. To enable XIP, the host MCU must support Quad SPI or QPI interface timing, the QE bit (Status Register-2, bit 1) must be set for Quad I/O, and the memory map must be configured to treat flash addresses as executable code space. The W25Q128FVBIG's 104MHz clock and 416MHz effective quad rate ensure sufficient bandwidth for real-time code fetch.

How many program/erase cycles does W25Q128FVBIG guarantee, and is this specified per sector or per device?

W25Q128FVBIG guarantees ≥100,000 program/erase cycles per individual 4KB sector, as confirmed in the "Features" section (page 5) and "Electrical Characteristics" (Section 9.6) of the official datasheet. This endurance rating is not averaged across the device but applies to each of the 4,096 uniform sectors independently, enabling wear-leveling algorithms in firmware to extend overall device lifetime beyond 1 million cycles in balanced usage patterns.

What is the purpose of the 64-bit Unique ID in W25Q128FVBIG, and how is it accessed?

The 64-bit Unique ID in W25Q128FVBIG is a factory-programmed, read-only serial number used for device authentication, traceability, and anti-cloning in secure systems. It is accessed via the Read Unique ID Number instruction (4Bh), requiring a 4-byte address (00h–03h) followed by 8 bytes of ID data. Unlike status or security registers, the Unique ID cannot be modified or erased, and is guaranteed unique across all W25Q128FVBIG units manufactured by Winbond.

Can W25Q128FVBIG's /WP pin provide hardware write protection when Quad SPI mode is enabled?

No, the /WP pin on W25Q128FVBIG does not provide hardware write protection when Quad SPI mode is enabled (QE = 1), because the /WP pin is reassigned as IO2 for quad data I/O. Hardware write protection remains available only in Standard and Dual SPI modes (QE = 0), where /WP is active-low and locks status register writes. Software-based protection using Block Protect (BP) bits and Status Register Protect (SRP) bits remains fully functional regardless of QE state and is recommended for Quad-mode systems.