Winbond Electronics Corporation W25Q128FVCIP
- Part No.:
- W25Q128FVCIP
- Manufacturer:
- Winbond Electronics Corporation
- Category:
- Memory
- Package:
- 24-TBGA
- Datasheet:
-
W25Q128FVCIP.pdf
- Description:
- IC FLASH 128MBIT SPI 24TFBGA
- Quantity:
- Payment:

- Shipping:

Inventory:3,458
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Product details
Overview
W25Q128FVCIP from Winbond is a 3.3V, 128M-bit (16MB) serial NOR flash memory IC supporting Standard/Dual/Quad SPI and QPI interfaces. It features 4KB uniform sectors, 104MHz max clock frequency, 50MB/s continuous read throughput, and operates across -40°C to +85°C. It serves as non-volatile program/data storage in microcontroller boot systems, firmware update modules, and embedded HMI displays.
For engineers reviewing the W25Q128FVCIP datasheet, W25Q128FVCIP pinout, W25Q128FVCIP application, or W25Q128FVCIP equivalent, key selection considerations include Quad Enable (QE) bit configuration for IO2/IO3 remapping, /HOLD vs /RESET pin behavior in 8-pin packages, sector-level write protection granularity, and SFDP register support for auto-configuration.
Technical Context
The W25Q128FVCIP implements a flexible SPI-compatible command set with hardware-accelerated erase/program suspend-resume, configurable output drive strength (DRV1/DRV0), and dual-mode /HOLD or /RESET functionality on Pin 7 of SOIC/VSOP/WSON/PDIP packages. Its status register includes volatile/non-volatile BP2–BP0, TB, SEC, CMP, SRP0/SRP1, QE, and WPS bits enabling fine-grained memory protection.
It supports true execute-in-place (XIP) via Continuous Read Mode with ≤8-clock instruction overhead and wrap lengths of 8/16/32/64 bytes. QPI mode reduces instruction overhead by encoding commands in 2-clock cycles, enabling 416MHz equivalent bandwidth using Quad I/O at 104MHz CLK.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 128 M-bit (16 MB), organized as 65,536 × 256-byte pages |
| Supply Voltage | 2.7 V to 3.6 V - compatible with 3.3 V logic systems without level shifting |
| Max Clock Frequency | 104 MHz - enables 416 Mbps Quad I/O read throughput in QPI mode |
| Erase Granularity | 4 KB sector / 32 KB block / 64 KB block / full chip - supports firmware partitioning and OTA updates |
| Write Endurance | 100,000 program/erase cycles per sector - suitable for field-upgradable embedded applications |
| Data Retention | 20 years at +85°C - validated for industrial temperature operation over product lifetime |
| Operating Temp | -40°C to +85°C - qualified for automotive infotainment and industrial control environments |
| Unique ID | 64-bit factory-programmed serial number - enables device authentication and secure provisioning |
Pinout & Package
W25Q128FVCIP uses an 8-pin SOIC 208-mil (Package Code S) with exposed pad, compliant with JEDEC MS-012AA. Pin 1 is /CS; Pin 2 is DO (IO1); Pin 3 is /WP (IO2); Pin 4 is GND; Pin 5 is DI (IO0); Pin 6 is CLK; Pin 7 is /HOLD or /RESET (IO3); Pin 8 is VCC.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| /CS (Pin 1) | Chip Select Input | Active-low enable: high-Z DO and standby current when high; required high-to-low transition after power-up before instruction acceptance |
| DO (IO1) (Pin 2) | Serial Data Output / Bidirectional I/O | Unidirectional output in Standard SPI; bidirectional data lane 1 in Dual/Quad SPI/QPI; requires QE=1 for Quad use |
| /WP (IO2) (Pin 3) | Hardware Write Protect / Bidirectional I/O | Active-low hardware lock for status register; repurposed as IO2 in Quad mode when QE=1; not available in QPI |
| GND (Pin 4) | Ground Reference | Primary return path for VCC and all I/O signals; must be low-impedance for stable timing and noise immunity |
| DI (IO0) (Pin 5) | Serial Data Input / Bidirectional I/O | Unidirectional input in Standard SPI; bidirectional data lane 0 in Dual/Quad SPI/QPI; always active in all modes |
| CLK (Pin 6) | Serial Clock Input | Edge-triggered timing reference: rising edge for input, falling edge for output; max 104 MHz; no internal PLL |
| /HOLD or /RESET (IO3) (Pin 7) | Hold Control or Reset Input / Bidirectional I/O | Active-low pause signal in Standard/Dual SPI; dedicated /RESET in 16-pin SOIC; becomes IO3 in Quad mode when QE=1 |
| VCC (Pin 8) | Power Supply | 2.7–3.6 V supply with typical 4 mA active and <1 µA power-down current; decoupling capacitor required near pin |
Key Features
| Feature | Design Value |
|---|---|
| Quad Peripheral Interface (QPI) | Reduces instruction overhead to 2 clocks per command, enabling deterministic XIP execution and eliminating opcode byte transfers |
| Continuous Read Mode | Supports 8/16/32/64-byte wrap with ≤8-clock address setup, minimizing latency for sequential code fetch in microcontroller boot loaders |
| Erase/Program Suspend-Resume | Allows background interrupt service routines to pause flash operations, preserving real-time system responsiveness during firmware updates |
| Three 256-byte Security Registers | OTP-lockable storage for cryptographic keys or calibration data, isolated from main array and inaccessible via standard read instructions |
| SFDP Register Support | JEDEC JESD216-compliant 16-byte parameter table enables automatic driver initialization without hard-coded timing or voltage assumptions |
| Top/Bottom Block Protection | Configurable via TB bit and BP2–BP0 to protect bootloader region (top) or application region (bottom) against accidental overwrite |
Applications
| Boot Memory for MCU-Based Systems | Firmware Update Storage |
|---|---|
|
Use Scenario: Storing boot code for ARM Cortex-M or RISC-V microcontrollers that execute directly from flash (XIP). IC Role / Device Role / Timing Role: Primary non-volatile code storage with deterministic 104MHz Quad SPI access and Continuous Read wrap for zero-wait-state execution. Use Value: Eliminates external RAM copy step, reduces BOM count, and cuts boot time by >30% versus parallel NOR flash in same footprint. |
Use Scenario: Holding signed firmware images for secure over-the-air (OTA) updates in IoT gateways and smart meters. IC Role / Device Role / Timing Role: Secure, field-upgradable storage with sector-level erase isolation and 64-bit unique ID for image binding. Use Value: Enables atomic update rollback and cryptographic verification without requiring full-chip erase, preserving configuration data across updates. |
| HMI Display Frame Buffer | Industrial PLC Configuration Storage |
|
Use Scenario: Caching bitmap assets and font glyphs for color TFT displays in medical devices and factory HMIs. IC Role / Device Role / Timing Role: High-throughput serial memory supporting burst reads up to 50 MB/s to feed display controllers via QSPI DMA. Use Value: Replaces slower SPI EEPROM or larger parallel NOR, reducing PCB area by 60% while sustaining 60 fps UI refresh rates. |
Use Scenario: Retaining ladder logic programs, I/O mapping tables, and calibration coefficients in programmable logic controllers. IC Role / Device Role / Timing Role: Industrial-grade non-volatile storage with 20-year data retention and -40°C to +85°C operation. Use Value: Guarantees configuration persistence through power cycling, brownouts, and thermal stress without battery backup. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial NOR flash memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MX25L12833FZC-10G | 104 MHz max clock, identical 128M-bit density and SOIC-8 package, but lacks QPI mode and SFDP register | No native QPI support limits XIP efficiency; requires custom driver for non-standard command set | Choose when QPI/XIP is unnecessary and legacy SPI-only interface suffices |
| S25FL128SAGMFI001 | 133 MHz max clock, 128M-bit density, supports Octal DTR mode (not supported by W25Q128FVCIP), different security register layout | Higher bandwidth potential but incompatible command set and OTP lock mechanism | Choose only if migrating to Cypress/Infineon ecosystem with Octal DTR requirement |
Compared with MX25L12833FZC-10G and S25FL128SAGMFI001, the W25Q128FVCIP delivers balanced performance with QPI-enabled XIP, JEDEC SFDP compliance, and field-proven 20-year retention-making it optimal for new designs prioritizing interoperability, security, and real-time execution.
Availability
W25Q128FVCIP is available at Aetrix Electronics and suitable for industrial control systems, automotive infotainment head units, and medical HMI displays requiring stable component supply, long-lifecycle support, and traceable sourcing.
Supply support for W25Q128FVCIP includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Winbond Electronics is a Taiwan-based semiconductor company specializing in specialty DRAM, mobile DRAM, and serial flash memory solutions since 1987.
The W25Q series targets cost-sensitive, space-constrained embedded systems needing high-speed, secure, and reliable non-volatile storage with minimal pin count and power budget.
FAQ
What is the package type and lead count of the W25Q128FVCIP?
The W25Q128FVCIP uses an 8-pin SOIC 208-mil package (JEDEC MS-012AA) with gull-wing leads and an exposed thermal pad. It is distinct from the 16-pin SOIC variant (W25Q128FVFIG) which adds a dedicated /RESET pin. The 'CIP' suffix confirms this specific SOIC-8 configuration.
Does the W25Q128FVCIP support Quad SPI and QPI modes simultaneously?
No. The W25Q128FVCIP supports Standard SPI, Dual SPI, Quad SPI, and QPI-but only one interface mode is active at a time. QPI mode is entered via the 0x38 instruction and exited with 0xFF; Quad SPI requires the QE bit (Status Register-2, Bit 1) to be set, repurposing Pins 3 (/WP) and 7 (/HOLD) as IO2 and IO3.
How does the /HOLD pin function differ between Standard SPI and Quad SPI modes on the W25Q128FVCIP?
In Standard SPI mode, Pin 7 functions as active-low /HOLD to pause ongoing read/write operations. In Quad SPI mode (QE=1), Pin 7 becomes IO3 and /HOLD is disabled. The W25Q128FVCIP does not support /HOLD in Quad mode-only the 16-pin SOIC variant offers independent /RESET alongside /HOLD.
Can the W25Q128FVCIP be used for secure firmware storage with cryptographic key protection?
Yes. The W25Q128FVCIP includes three 256-byte Security Registers with One-Time-Programmable (OTP) lock bits (LB1–LB3). Once locked, these registers are read-only and inaccessible via standard read instructions-providing tamper-resistant storage for AES keys, device certificates, or calibration secrets.
What is the role of the SFDP register in the W25Q128FVCIP, and how is it accessed?
The SFDP (Serial Flash Discoverable Parameters) register is a JEDEC JESD216-compliant 16-byte table containing timing, voltage, and command-set metadata. It is read using instruction 0x5A and enables host drivers to auto-configure without hardcoded parameters-critical for portable, multi-vendor flash abstraction layers in RTOS and Linux kernel drivers.
W25Q128FVCIP Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Winbond Electronics Corporation
- Series:
- SpiFlash®
- Package/Case:
- 24-TBGA
- Packaging:
- Tube
- Product Status:
- Discontinued at Digi-Key
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH - NOR
- Memory Size:
- 128Mbit
- Memory Organization:
- 16M x 8
- Memory Interface:
- SPI - Quad I/O, QPI
- Clock Frequency:
- 104 MHz
- Write Cycle Time - Word, Page:
- 50µs, 3ms
- Access Time:
- -
- Voltage - Supply:
- 2.7V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 24-TFBGA (6x8)
W25Q128FVCIP FAQ
1.How can I place an order for W25Q128FVCIP through Aetrix?
Please submit a Request for Quotation (RFQ) for W25Q128FVCIP on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for W25Q128FVCIP reliable?
The price and inventory of W25Q128FVCIP are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for W25Q128FVCIP is usually 5 days.
3.What payment methods are accepted for W25Q128FVCIP?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for W25Q128FVCIP transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for W25Q128FVCIP?
W25Q128FVCIP orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your W25Q128FVCIP order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for W25Q128FVCIP?
For technical support, including W25Q128FVCIP datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your W25Q128FVCIP requirements.
6.How does Aetrix verify that W25Q128FVCIP is sourced from the original manufacturer or authorized distributors?
All W25Q128FVCIP products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that W25Q128FVCIP meets industry standards.
7.What is the process for return or replacement of W25Q128FVCIP?
All W25Q128FVCIP units undergo pre-shipment inspection (PSI). If there is an issue with W25Q128FVCIP, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The W25Q128FVCIP part is unused and in its original packaging.
Return procedure for W25Q128FVCIP:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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