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Winbond Electronics Corporation W25Q128FVCJQ
- Part No.:
- W25Q128FVCJQ
- Manufacturer:
- Winbond Electronics Corporation
- Category:
- Memory
- Package:
- 24-TBGA
- Datasheet:
-
W25Q128FVCJQ.pdf
- Description:
- IC FLASH 128MBIT SPI 24TFBGA
- Quantity:
- Payment:
- Shipping:
Inventory:2,779
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Product details
Overview
W25Q128FVCJQ from Winbond is a 128M-bit (16MB) serial NOR flash memory supporting Standard/Dual/Quad SPI and QPI interfaces, operating at 2.7–3.6V with 104MHz max clock, 4KB uniform sector erase granularity, and 1µA typical power-down current. It enables XIP (execute-in-place) code execution in embedded microcontrollers, firmware storage in industrial controllers, and parameter logging in IoT edge nodes.
For engineers reviewing the W25Q128FVCJQ datasheet, W25Q128FVCJQ pinout, W25Q128FVCJQ application, or W25Q128FVCJQ equivalent, key selection criteria include Quad SPI bandwidth (416MHz equivalent), JEDEC SFDP register support for auto-configuration, 64-bit unique ID for device authentication, and hardware write protection via /WP and /HOLD pins in standard mode.
Technical Context
The W25Q128FVCJQ implements a flexible SPI-compatible memory architecture with dual-mode I/O: standard unidirectional DI/DO pins for legacy SPI, and bidirectional IO0–IO3 for Dual/Quad SPI and QPI. Its status register includes non-volatile Quad Enable (QE) bit that reassigns /WP and /HOLD to IO2 and IO3 respectively-enabling 4-line data transfer but disabling hardware write/halt control.
It supports three erase granularities-4KB sectors (4,096 total), 32KB blocks (512), and 64KB blocks (256)-and features volatile/non-volatile block protect bits (BP2–BP0), top/bottom array control (TB), and security registers with OTP locks. The /RESET pin is dedicated only in 16-pin SOIC packages; in 8-pin variants like W25Q128FVCJQ, /HOLD and /RESET share IO3 and are selected via Status Register configuration.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 128 M-bit (16 MB), organized as 65,536 × 256-byte pages |
| Interface Modes | Standard SPI (4-wire), Dual SPI (2 I/O lines), Quad SPI (4 I/O lines), QPI (4-wire full-duplex) |
| Max Clock Frequency | 104 MHz (SPI), enabling 208 MB/s Dual I/O and 416 MB/s Quad I/O effective throughput |
| Erase Granularity | Uniform 4KB sectors (4,096 sectors), plus 32KB/64KB blocks-supports fine-grained firmware partitioning |
| Write/Erase Endurance | 100,000 program/erase cycles per sector, ensuring long-term reliability in field-updatable systems |
| Data Retention | 20 years at +25°C, validated for industrial temperature range (−40°C to +85°C) |
| Power Supply | Single 2.7–3.6V supply; active current ≤4 mA, power-down current ≤1 µA (typ.) |
| Security Features | 64-bit unique ID, JEDEC SFDP register, three 256-byte OTP-lockable security registers |
Pinout & Package
W25Q128FVCJQ uses an 8-pin WSON 6×5-mm package (Package Code P), with exposed pad for thermal dissipation. Pin 1 is /CS; pins 2–3 and 5–8 are bidirectional I/Os or function-selectable control inputs depending on interface mode.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 /CS | Chip Select Input | Active-low enable: high = device deselected (high-Z outputs, standby current); low = active communication |
| 2 DO (IO1) | Data Output / I/O Line 1 | Unidirectional output in Standard SPI; bidirectional in Dual/Quad SPI/QPI; used for read data and status |
| 3 /WP (IO2) | Write Protect Input / I/O Line 2 | Hardware lock for status register when QE=0; becomes IO2 in Quad mode (QE=1), disabling write protection |
| 4 GND | Ground Reference | Signal and power return path; must be low-impedance for stable timing and noise immunity |
| 5 DI (IO0) | Data Input / I/O Line 0 | Unidirectional input in Standard SPI; bidirectional in Dual/Quad SPI/QPI; carries instructions, addresses, write data |
| 6 CLK | Serial Clock Input | Master-generated clock; rising edge latches input, falling edge samples output; determines max interface speed |
| 7 /HOLD or /RESET (IO3) | Hold/Reset Input / I/O Line 3 | Pauses ongoing operation when low (QE=0); becomes IO3 in Quad mode (QE=1); reset function requires QE=0 and SR bit setting |
| 8 VCC | Power Supply | 2.7–3.6V single supply; decoupling capacitor required near pin for transient current stability |
Key Features
| Feature | Design Value |
|---|---|
| Continuous Read Mode | As few as 8 clocks overhead to initiate address fetch-enables deterministic XIP latency for real-time code execution |
| Quad Peripheral Interface (QPI) | Reduces instruction overhead by using 4-wire full-duplex protocol-eliminates separate instruction/address phases for burst reads |
| Volatile & Non-Volatile Status Control | BP2–BP0, TB, SEC, CMP bits configurable in both volatile (power-cycle loss) and non-volatile (flash-persistent) modes for flexible protection schemes |
| Erase/Program Suspend & Resume | Allows background operations (e.g., logging) to pause flash writes-prevents system stalls during critical real-time tasks |
| JEDEC SFDP Register | Standardized, read-only register providing vendor-independent parameter tables-enables automatic driver initialization without hard-coded timing values |
| OTP-Lockable Security Registers | Three 256-byte regions with one-time-programmable locks-used for secure key storage, calibration data, or firmware signature verification |
Applications
| Industrial PLC Firmware Storage | Automotive ADAS Boot Image |
|---|---|
|
Use Scenario: Storing boot firmware and configuration parameters in programmable logic controllers deployed in factory automation environments with wide temperature swings and EMI exposure. IC Role / Device Role / Timing Role: Primary non-volatile code storage device interfaced directly to ARM Cortex-M7 MCU via Quad SPI at 80MHz for sub-100ms boot time. Use Value: 4KB sector erase allows independent update of safety-critical firmware partitions without disturbing runtime configuration data stored in adjacent sectors. |
Use Scenario: Holding boot loader and sensor fusion firmware for automotive camera-based ADAS modules requiring AEC-Q100 Grade 2 qualification and secure boot validation. IC Role / Device Role / Timing Role: Secure boot source providing authenticated, encrypted firmware images to SoC via QPI interface with hardware-accelerated decryption handshake. Use Value: 64-bit unique ID and OTP-locked security registers enable cryptographic binding of firmware image to specific hardware unit-preventing cloning or unauthorized reflashing. |
| Medical Infusion Pump Parameter Log | Smart Meter Firmware & Calibration Data |
|
Use Scenario: Logging dose history, error events, and calibration drift in Class II medical infusion pumps subject to FDA 21 CFR Part 11 audit requirements. IC Role / Device Role / Timing Role: Secondary non-volatile data logger co-located with main MCU, using sector-protected regions for tamper-evident event timestamps and user-accessible logs. Use Value: Hardware write protection (/WP pin + BP bits) ensures critical audit trail cannot be overwritten-even during firmware updates-meeting regulatory integrity mandates. |
Use Scenario: Storing metrology firmware, tariff tables, and factory calibration coefficients in ANSI C12.22-compliant smart electricity meters deployed in utility substations. IC Role / Device Role / Timing Role: Dual-role memory: executes metering algorithms via XIP while retaining field-upgradable calibration data in isolated 4KB sectors. Use Value: 20-year data retention and 100K endurance guarantee accurate billing data persistence across 15+ year product lifecycles without battery backup. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial NOR flash memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MX25L12833FZNI-10G | 128Mb density, 104MHz max clock, but lacks QPI mode and SFDP register; uses different status register layout and no unique ID | Supports only Standard/Dual/Quad SPI-not suitable for QPI-based XIP designs requiring minimal instruction overhead | Select when QPI is unnecessary and cost sensitivity outweighs configurability needs; verify /WP and /HOLD behavior differs in Quad mode |
| S25FL128SAGMFI000 | 128Mb, 133MHz clock, supports HyperBus interface (not SPI-compatible), includes ECC and configurable dummy cycles | Requires HyperFlash controller-not interoperable with standard SPI masters; targets high-reliability aerospace/defense where ECC is mandatory | Choose only if migrating to Cypress/Infineon ecosystem with HyperBus-capable SoC; not a drop-in replacement for SPI-based designs |
Compared with W25Q128FVCJQ, MX25L12833FZNI-10G offers identical density and speed but omits QPI and SFDP-limiting auto-configuration and XIP efficiency-while S25FL128SAGMFI000 introduces incompatible HyperBus signaling and ECC overhead, making it unsuitable for direct SPI substitution despite matching capacity.
Availability
W25Q128FVCJQ is available at Aetrix Electronics and suitable for industrial PLC firmware storage, automotive ADAS boot image retention, and medical infusion pump parameter logging requiring stable component supply across extended product lifecycles.
Supply support for W25Q128FVCJQ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Winbond Electronics is a Taiwan-based semiconductor manufacturer specializing in specialty memory solutions, including serial flash, RAM, and mobile DRAM, with global manufacturing and quality certifications.
The W25Q series targets embedded systems requiring high-speed, low-power, and secure non-volatile storage-designed specifically for code execution, firmware updates, and trusted data logging in resource-constrained environments.
FAQ
What interface modes does the W25Q128FVCJQ support, and how is Quad SPI enabled?
The W25Q128FVCJQ supports Standard SPI, Dual SPI, Quad SPI, and QPI. Quad SPI mode is activated by setting the non-volatile Quad Enable (QE) bit in Status Register-2 (SR2). When QE=1, pins /WP and /HOLD become IO2 and IO3 respectively-enabling four-line bidirectional data transfer. This configuration disables hardware write protection and hold functionality, requiring software-managed equivalents.
Does the W25Q128FVCJQ have a dedicated /RESET pin, and how is it accessed?
No, the W25Q128FVCJQ does not have a dedicated /RESET pin-it uses an 8-pin WSON package where pin 7 serves as /HOLD or /RESET depending on Status Register configuration. When QE=0 and the HOLD/RST bit is set, pin 7 functions as /RESET; when QE=1, it operates as IO3 in Quad mode and /RESET is unavailable. For guaranteed reset capability, use the 16-pin SOIC variant (e.g., W25Q128FVFIG).
How does the W25Q128FVCJQ implement hardware write protection, and what happens in Quad SPI mode?
Hardware write protection on the W25Q128FVCJQ is implemented via the /WP pin (pin 3), which-when held low-prevents writes to the status register. This works only when QE=0. In Quad SPI mode (QE=1), /WP is reassigned as IO2, disabling hardware write protection. Protection must then rely on software-configured status register bits (BP2–BP0, TB, SEC) and OTP-locked security registers.
What is the significance of the 64-bit Unique ID and SFDP register in the W25Q128FVCJQ?
The 64-bit Unique ID provides cryptographically verifiable device identity-essential for secure boot, anti-cloning, and firmware binding in regulated applications. The JEDEC SFDP register contains standardized, read-only parameter tables (e.g., erase timings, voltage ranges) that allow host drivers to auto-configure without hardcoded values-reducing porting effort across platforms and improving robustness against datasheet version mismatches.
Can the W25Q128FVCJQ perform concurrent read and program/erase operations?
No, the W25Q128FVCJQ does not support true concurrent read-while-write (RWW). However, it supports Erase/Program Suspend and Resume: an active program or erase operation can be paused via 75h instruction to service a high-priority read request, then resumed with 7Ah. This minimizes system latency impact without requiring full operation cancellation or reinitialization.
W25Q128FVCJQ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Winbond Electronics Corporation
- Series:
- SpiFlash®
- Package/Case:
- 24-TBGA
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH - NOR
- Memory Size:
- 128Mbit
- Memory Organization:
- 16M x 8
- Memory Interface:
- SPI - Quad I/O, QPI
- Clock Frequency:
- 104 MHz
- Write Cycle Time - Word, Page:
- 50µs, 3ms
- Access Time:
- -
- Voltage - Supply:
- 2.7V ~ 3.6V
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 24-TFBGA (6x8)
W25Q128FVCJQ FAQ
1.How can I place an order for W25Q128FVCJQ through Aetrix?
Please submit a Request for Quotation (RFQ) for W25Q128FVCJQ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for W25Q128FVCJQ reliable?
The price and inventory of W25Q128FVCJQ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for W25Q128FVCJQ is usually 5 days.
3.What payment methods are accepted for W25Q128FVCJQ?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for W25Q128FVCJQ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for W25Q128FVCJQ?
W25Q128FVCJQ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your W25Q128FVCJQ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for W25Q128FVCJQ?
For technical support, including W25Q128FVCJQ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your W25Q128FVCJQ requirements.
6.How does Aetrix verify that W25Q128FVCJQ is sourced from the original manufacturer or authorized distributors?
All W25Q128FVCJQ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that W25Q128FVCJQ meets industry standards.
7.What is the process for return or replacement of W25Q128FVCJQ?
All W25Q128FVCJQ units undergo pre-shipment inspection (PSI). If there is an issue with W25Q128FVCJQ, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The W25Q128FVCJQ part is unused and in its original packaging.
Return procedure for W25Q128FVCJQ:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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