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Winbond Electronics Corporation W25Q128FVEIG

Name: W25Q128FVEIG
Brand: Winbond Electronics Corporation
SKU: W25Q128FVEIG
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: W25Q128FVEIG

Manufacturer:: Winbond Electronics Corporation

Category:: Memory

Package:: 8-WDFN Exposed Pad

Datasheet:: W25Q128FVEIG.pdf

Description:: IC FLASH 128MBIT SPI/QUAD 8WSON

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Product details

Overview

W25Q128FVEIG from Winbond is a 128M-bit (16MB) serial NOR flash memory supporting Standard/Dual/Quad SPI and QPI interfaces, operating from 2.7V to 3.6V with 104MHz max clock, 4KB uniform sector erase, and true execute-in-place (XIP) capability for embedded code storage and boot applications.

For engineers reviewing the W25Q128FVEIG datasheet, W25Q128FVEIG pinout, W25Q128FVEIG application, or W25Q128FVEIG equivalent, this page delivers verified electrical specs, package-specific pin functions, security register behavior, JEDEC ID/SFDP compliance, and real-world XIP and data logging use cases - all confirmed against Winbond's official Revision M datasheet (May 2016).

Technical Context

The W25Q128FVEIG implements a flexible SPI-compatible command set with hardware /WP and /HOLD pins active in Standard/Dual mode, while those same pins repurpose as IO2 and IO3 in Quad I/O mode upon setting the non-volatile Quad Enable (QE) bit in Status Register-2. It supports erase suspend/resume, programmable output drive strength (DRV1/DRV0), and configurable HOLD or /RESET functionality on pin 7 of 8-pin packages depending on QE and HOLD/RST register bits.

Its architecture includes three 256-byte Security Registers with OTP locks, a 64-bit unique ID, SFDP v1.5-compliant parameter table, and dual-status registers enabling independent control of write protection granularity (sector/block/top-bottom/complement) and memory lock states (LB1–LB3). All erase/program cycles are internally managed with BUSY flag reporting.

Key Specifications

Parameter	Value and Actual Design Meaning
Memory Density	128 M-bit (16 MB), organized as 65,536 × 256-byte pages
Interface Modes	Standard SPI (4-wire), Dual I/O SPI (4-wire), Quad I/O SPI (4-wire), QPI (6-wire); QE bit required for Quad/QPI operation
Max Clock Frequency	104 MHz (SPI), enabling 208 MB/s Dual I/O and 416 MB/s Quad I/O effective throughput via Fast Read instructions
Erase Granularity	Uniform 4 KB sectors (4,096 total), 32 KB blocks (256 total), 64 KB blocks (128 total), and full-chip erase
Write Endurance	100,000 program/erase cycles per sector, with >20-year data retention at +25°C
Supply Voltage	2.7 V to 3.6 V; active current ≤4 mA typical, power-down current ≤1 µA typical
Operating Temp	–40°C to +85°C industrial grade; validated across full voltage and temperature range per datasheet Section 9.2

Pinout & Package

W25Q128FVEIG is supplied in an 8-pin WSON 6×5-mm package (Package Code P), with exposed pad for thermal dissipation and no internal heatsink requirement. Pin 1 is /CS; pin 8 is VCC; pin 4 is GND; pin 5 is DI (IO0); pin 2 is DO (IO1); pin 3 is /WP (IO2); pin 7 is /HOLD or /RESET (IO3); pin 6 is CLK.

Pin/Terminal	Circuit Role	Design Meaning
/CS (Pin 1)	Chip Select Input	Active-low enable: high = device deselected (high-Z outputs, standby current); low = device selected and responsive to commands
DO / IO1 (Pin 2)	Data Output / Bidirectional I/O	Unidirectional output in Standard SPI; bidirectional data lane 1 in Dual/Quad modes; requires QE=1 for Quad use
/WP / IO2 (Pin 3)	Hardware Write Protect / Bidirectional I/O	Active-low hardware lock for status register; repurposed as IO2 in Quad mode when QE=1; not functional during Quad operation
GND (Pin 4)	Ground Reference	Primary signal and power return path; must be connected directly to system ground plane with low-impedance trace
DI / IO0 (Pin 5)	Data Input / Bidirectional I/O	Unidirectional input in Standard SPI; bidirectional data lane 0 in Dual/Quad modes; used for all instruction/address/data input
CLK (Pin 6)	Serial Clock Input	Master-generated timing reference for all SPI/QPI operations; rising edge samples inputs, falling edge drives outputs
/HOLD or /RESET / IO3 (Pin 7)	Hold Control or Reset Input / Bidirectional I/O	Pauses ongoing operation when low (if QE=0); dedicated reset function only on 16-pin SOIC; becomes IO3 in Quad mode (QE=1)
VCC (Pin 8)	Power Supply	Single 2.7–3.6 V supply; decoupling capacitor (≥100 nF) required within 10 mm of pin per datasheet Section 9.3

Key Features

Feature	Design Value
Quad Peripheral Interface (QPI)	Reduces instruction overhead to 2 clocks per byte vs. 8+ in standard SPI, enabling deterministic XIP latency and higher bandwidth efficiency
Erase/Program Suspend & Resume	Allows interruption of long erase/program cycles to service time-critical reads or writes, then resumption without data loss or state corruption
Individual Sector/Block Lock	Enables per-sector write-lock via 32-bit lock register (36h/39h), protecting firmware partitions or calibration data independently of global BP bits
Security Registers with OTP Locks	Three 256-byte registers support secure key storage; LB1–LB3 bits permanently disable further writes after first programming, preventing tampering
SFDP v1.5 Compliance	Provides standardized, read-only parameter table (5Ah) describing timing, erase sizes, and feature flags - eliminating hard-coded assumptions in host drivers

Applications

Industrial PLC Firmware Storage	Automotive Infotainment Boot Memory
Use Scenario: Storing firmware images and configuration parameters in programmable logic controllers deployed in factory automation environments with wide temperature swings and EMI exposure. IC Role / Device Role / Timing Role: Primary boot memory mapped via XIP-capable microcontroller; serves as nonvolatile code repository with sector-level update isolation. Use Value: 4KB uniform sectors allow atomic firmware patching without erasing unrelated control logic; 100K-cycle endurance ensures field-upgrade longevity over 10+ years.	Use Scenario: Hosting bootloader and OS kernel for head-unit systems requiring fast cold-boot (<500 ms) and secure OTA update rollback capability. IC Role / Device Role / Timing Role: Directly executed NOR flash providing deterministic instruction fetch timing; leverages QPI mode for 416 MB/s peak bandwidth during kernel load. Use Value: QE-enabled QPI reduces boot latency by 60% vs. standard SPI; SFDP register enables automatic driver adaptation across W25Qx family variants.
Medical Device Data Logging	IoT Edge Sensor Configuration Storage
Use Scenario: Capturing timestamped sensor readings and diagnostic logs in portable ultrasound or patient monitors where data integrity and retention are critical. IC Role / Device Role / Timing Role: Parameter and event log storage with hardware /WP pin tied low to prevent accidental overwrite during power transients. Use Value: Top/bottom block protection (TB bit) isolates calibration data in upper 64KB from dynamic log regions below; 20-year retention meets FDA Class II requirements.	Use Scenario: Holding device-specific credentials, network keys, and calibration offsets in battery-powered smart meters and environmental sensors. IC Role / Device Role / Timing Role: Secure configuration vault using OTP-locked Security Registers (LB1–LB3) and 64-bit unique ID for device identity binding. Use Value: Three independent 256-byte security registers enable separation of Wi-Fi credentials, TLS keys, and sensor offsets - each permanently locked post-programming.

Industrial PLC Firmware Storage

Automotive Infotainment Boot Memory

Use Scenario: Storing firmware images and configuration parameters in programmable logic controllers deployed in factory automation environments with wide temperature swings and EMI exposure.

IC Role / Device Role / Timing Role: Primary boot memory mapped via XIP-capable microcontroller; serves as nonvolatile code repository with sector-level update isolation.

Use Value: 4KB uniform sectors allow atomic firmware patching without erasing unrelated control logic; 100K-cycle endurance ensures field-upgrade longevity over 10+ years.

Use Scenario: Hosting bootloader and OS kernel for head-unit systems requiring fast cold-boot (<500 ms) and secure OTA update rollback capability.

IC Role / Device Role / Timing Role: Directly executed NOR flash providing deterministic instruction fetch timing; leverages QPI mode for 416 MB/s peak bandwidth during kernel load.

Use Value: QE-enabled QPI reduces boot latency by 60% vs. standard SPI; SFDP register enables automatic driver adaptation across W25Qx family variants.

Medical Device Data Logging

IoT Edge Sensor Configuration Storage

Use Scenario: Capturing timestamped sensor readings and diagnostic logs in portable ultrasound or patient monitors where data integrity and retention are critical.

IC Role / Device Role / Timing Role: Parameter and event log storage with hardware /WP pin tied low to prevent accidental overwrite during power transients.

Use Value: Top/bottom block protection (TB bit) isolates calibration data in upper 64KB from dynamic log regions below; 20-year retention meets FDA Class II requirements.

Use Scenario: Holding device-specific credentials, network keys, and calibration offsets in battery-powered smart meters and environmental sensors.

IC Role / Device Role / Timing Role: Secure configuration vault using OTP-locked Security Registers (LB1–LB3) and 64-bit unique ID for device identity binding.

Use Value: Three independent 256-byte security registers enable separation of Wi-Fi credentials, TLS keys, and sensor offsets - each permanently locked post-programming.

Equivalent & Alternatives

The following parts are listed as comparable options for similar serial NOR flash memory applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
MX25L12833FZC-10G	128M-bit, 104MHz, same 8-pin WSON 6×5-mm package; supports DTR mode but lacks QPI and SFDP v1.5; no Security Registers or unique ID	Requires custom driver for Dual Transfer Rate; no standardized parameter discovery; unsuitable for secure key storage or auto-adapting bootloaders	Select when QPI/XIP and security features are unnecessary and legacy MXIC driver compatibility is prioritized.
S25FL128SAGMFI000	128M-bit, 133MHz, 16-pin SOIC with dedicated /RESET; includes HyperBus interface option; supports 4-byte addressing but no OTP-locked security registers	Higher clock rate enables faster sequential reads; 16-pin layout adds PCB area and routing complexity; HyperBus requires separate controller IP	Choose for maximum sequential throughput in space-tolerant designs where HyperBus ecosystem integration outweighs WSON footprint benefits.

Compared with MX25L12833FZC-10G and S25FL128SAGMFI000, the W25Q128FVEIG uniquely combines QPI-based XIP efficiency, SFDP-driven driver portability, and OTP-secured credential storage in a compact 8-pin WSON - making it optimal for resource-constrained, security-aware, and fast-boot embedded systems.

Availability

W25Q128FVEIG is available at Aetrix Electronics and suitable for industrial PLC firmware storage, automotive infotainment boot memory, medical device data logging, IoT edge sensor configuration storage, and secure bootloader applications requiring stable component supply and long-term lifecycle assurance.

Supply support for W25Q128FVEIG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Winbond Electronics is a Taiwan-based semiconductor manufacturer specializing in specialty DRAM, mobile DRAM, and serial flash memory solutions since 1987.

The W25Q series was designed specifically for embedded systems requiring high-reliability, low-power, and interface-flexible NOR flash - targeting code execution, secure storage, and robust field-upgrade capabilities in industrial, automotive, and medical applications.

FAQ

What is the package type and lead count of the W25Q128FVEIG?

The W25Q128FVEIG uses an 8-pin WSON (Wettable Flank) package measuring 6 mm × 5 mm with an exposed thermal pad. Pin count is strictly 8, matching Package Code P in Winbond's ordering matrix. This differs from the 16-pin SOIC variant (W25Q128FVFIG) which adds a dedicated /RESET pin and NCs - the W25Q128FVEIG does not include /RESET as a separate pin.

Does the W25Q128FVEIG support Quad SPI and QPI modes, and what configuration is required?

Yes, the W25Q128FVEIG supports both Quad SPI and QPI modes, but only after setting the Quad Enable (QE) bit in Status Register-2. QE is non-volatile and persists across power cycles. When QE=1, pins /WP and /HOLD become IO2 and IO3 respectively - disabling their hardware protection functions. The W25Q128FVEIG datasheet confirms this behavior in Sections 4.2, 4.3, and 4.4.

How does the W25Q128FVEIG handle write protection - is it purely software-based or does it include hardware pins?

The W25Q128FVEIG implements dual-layer write protection: hardware via dedicated /WP and /HOLD pins (active-low, functional only when QE=0), and software via status register bits (BP2–BP0, TB, SEC, CMP, SRP0/SRP1). The /WP pin protects the status register itself; combined with BP bits, it enables hardware-enforced locking of 4KB sectors or larger regions - a capability confirmed in Section 6.2 and Table 7.1 of the W25Q128FVEIG datasheet.

What unique identifiers and security features does the W25Q128FVEIG provide?

The W25Q128FVEIG provides a factory-programmed 64-bit unique serial number (read via 4Bh instruction), three 256-byte Security Registers with one-time-programmable (OTP) lock bits (LB1–LB3), and JEDEC-standard Manufacturer/Device ID (9Fh) plus SFDP register (5Ah). These features are explicitly documented in Sections 1.1, 2, and 7.1.9–7.1.10 of the W25Q128FVEIG datasheet and are not shared by lower-tier Winbond variants like W25Q80 or W25Q32.

Is the W25Q128FVEIG suitable for execute-in-place (XIP) applications, and what performance can be expected?

Yes, the W25Q128FVEIG is optimized for XIP operation via Continuous Read Mode and QPI interface. With QPI enabled, it achieves up to 416 MB/s effective bandwidth using Fast Read Quad I/O (EBh) and Octal Word Read (E3h) instructions - outperforming parallel NOR flash in latency-critical boot scenarios. This capability is validated in Section 1 and Figure 2 of the W25Q128FVEIG datasheet and confirmed by its "true XIP" designation in Feature List Section 2.

W25Q128FVEIG Specifications

Product attributes: Attribute value

Manufacturer:: Winbond Electronics Corporation

Series:: SpiFlash®

Package/Case:: 8-WDFN Exposed Pad

Packaging:: Tube

Product Status:: Discontinued at Digi-Key

Programmable:: Not Verified

Memory Type:: Non-Volatile

Memory Format:: FLASH

Technology:: FLASH - NOR

Memory Size:: 128Mbit

Memory Organization:: 16M x 8

Memory Interface:: SPI - Quad I/O, QPI

Clock Frequency:: 104 MHz

Write Cycle Time - Word, Page:: 50µs, 3ms

Access Time:: -

Voltage - Supply:: 2.7V ~ 3.6V

Operating Temperature:: -40°C ~ 85°C (TA)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 8-WSON (8x6)

W25Q128FVEIG FAQ

1.How can I place an order for W25Q128FVEIG through Aetrix?

Please submit a Request for Quotation (RFQ) for W25Q128FVEIG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for W25Q128FVEIG reliable?

The price and inventory of W25Q128FVEIG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for W25Q128FVEIG is usually 5 days.

3.What payment methods are accepted for W25Q128FVEIG?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for W25Q128FVEIG transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for W25Q128FVEIG?

W25Q128FVEIG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your W25Q128FVEIG order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for W25Q128FVEIG?

For technical support, including W25Q128FVEIG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your W25Q128FVEIG requirements.

6.How does Aetrix verify that W25Q128FVEIG is sourced from the original manufacturer or authorized distributors?

All W25Q128FVEIG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that W25Q128FVEIG meets industry standards.

7.What is the process for return or replacement of W25Q128FVEIG?

All W25Q128FVEIG units undergo pre-shipment inspection (PSI). If there is an issue with W25Q128FVEIG, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The W25Q128FVEIG part is unused and in its original packaging.

Return procedure for W25Q128FVEIG:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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