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Winbond Electronics Corporation W25Q128FVEIG TR
- Part No.:
- W25Q128FVEIG TR
- Manufacturer:
- Winbond Electronics Corporation
- Category:
- Memory
- Package:
- 8-WDFN Exposed Pad
- Datasheet:
-
W25Q128FVEIG TR.pdf
- Description:
- IC FLASH 128MBIT SPI/QUAD 8WSON
- Quantity:
- Payment:
- Shipping:
Inventory:2,409
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Product details
Overview
W25Q128FVEIG TR from Winbond is a 128M-bit (16MB) serial NOR flash memory supporting Standard/Dual/Quad SPI and QPI interfaces, operating at 2.7–3.6V with 104MHz max clock, 4KB uniform sectors, and hardware write protection via /WP and /HOLD pins. It enables XIP execution in embedded boot code storage, firmware update storage, and parameter retention in industrial controllers.
For engineers reviewing the W25Q128FVEIG TR datasheet, W25Q128FVEIG TR pinout, W25Q128FVEIG TR application, or W25Q128FVEIG TR equivalent, this page delivers verified package mapping (8-pin WSON 6×5-mm), confirmed Quad Enable (QE) bit behavior, JEDEC ID support, 50MB/s continuous read throughput, and real-world sector/block erase flexibility for firmware partitioning.
Technical Context
The W25Q128FVEIG TR implements a flexible SPI-compatible command set with volatile/non-volatile status register control (SRP0/SRP1, BP0–BP2, TB, SEC, QE), enabling selective 4KB sector, 32KB block, 64KB block, or full-chip erase. Its dual-function IO pins (IO0–IO3) reconfigure based on QE bit state: IO2 and IO3 become active only when QE=1, disabling /WP and /HOLD functionality in Quad mode.
It supports Erase/Program Suspend & Resume for concurrent background operations, 64-bit unique ID per device, three 256-byte security registers with OTP locks, and SFDP register for discoverable timing and feature parameters - all compliant with JEDEC JESD216B. The /RESET pin is dedicated in 16-pin SOIC but shared with /HOLD on 8-pin packages depending on SR configuration.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 128 M-bit (16 MB), organized as 65,536 × 256-byte pages |
| Interface Modes | Standard SPI (4-wire), Dual I/O SPI, Quad I/O SPI, and QPI (6-wire); QE bit controls IO2/IO3 activation |
| Max Clock Frequency | 104 MHz (SPI), enabling 208 MHz effective (Dual I/O) and 416 MHz effective (Quad I/O) data rates |
| Erase Granularity | Uniform 4 KB sectors (4,096 total), 32 KB blocks (256), 64 KB blocks (128), and chip-erase (C7h/60h) |
| Write Endurance | ≥100,000 program/erase cycles per sector, with ≥20-year data retention at +25°C |
| Power Supply | Single 2.7 V to 3.6 V supply; typical active current 4 mA, power-down current <1 µA |
| Operating Temp | –40°C to +85°C industrial grade, qualified per AEC-Q100 not applicable (non-automotive) |
Pinout & Package
W25Q128FVEIG TR uses the 8-pad WSON 6×5-mm package (Package Code P), with wettable flank leads for automated optical inspection. Pin 1 is marked by a dot; pinout is identical to SOIC/VSOP 208-mil but in surface-mount form.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| /CS | Chip Select Input | Active-low enable; high-impedance DO/IOs when deasserted; required high→low transition after power-up before instruction acceptance |
| DO (IO1) | Data Output / Bidirectional I/O | Unidirectional output in Standard SPI; bidirectional in Dual/Quad modes; used for status/data reads on CLK falling edge |
| /WP (IO2) | Write Protect Input / Bidirectional I/O | Active-low hardware lock for Status Register; disabled as /WP and repurposed as IO2 when QE=1 in Quad mode |
| GND | Ground Reference | Primary signal and power return path; decoupling capacitor must be placed near VCC–GND pins |
| DI (IO0) | Data Input / Bidirectional I/O | Unidirectional input in Standard SPI; bidirectional in Dual/Quad modes; carries instructions/addresses/data on CLK rising edge |
| CLK | Serial Clock Input | Master-generated timing reference; all SPI/QPI transfers synchronized to rising/falling edges per mode |
| /HOLD or /RESET (IO3) | Hold/Reset Input / Bidirectional I/O | Pauses ongoing operation when low (/HOLD); resets internal logic when pulsed (/RESET); becomes IO3 only when QE=1 |
| VCC | Power Supply | 2.7–3.6 V core supply; requires local 100 nF ceramic decoupling between VCC and GND |
Key Features
| Feature | Design Value |
|---|---|
| Continuous Read Mode | As few as 8 clocks overhead to initiate read; supports 8/16/32/64-byte wrap for burst efficiency and true XIP operation |
| Quad Peripheral Interface (QPI) | Reduces instruction overhead vs. standard SPI; enables 4-line data transfer with single-cycle addressing, improving throughput over Dual SPI |
| Erase/Program Suspend & Resume | Allows interruption of long erase/program cycles to service higher-priority reads or writes, then resume without data loss |
| Security Registers | Three 256-byte OTP-lockable registers for secure key storage, calibration data, or cryptographic seeds - inaccessible after lock |
| JEDEC & SFDP Compliance | Supports standardized Manufacturer/Device ID (90h/9Fh), Unique ID (4Bh), and SFDP register (5Ah) for automated configuration discovery |
Applications
| Boot Code Storage | Firmware Update Storage |
|---|---|
|
Use Scenario: Storing primary bootloader and application firmware for microcontrollers in industrial gateways. IC Role / Device Role / Timing Role: Non-volatile code storage with XIP capability; accessed via Quad SPI for fast startup and deterministic latency. Use Value: Enables sub-100ms cold boot via 416MHz-equivalent Quad I/O read speed and Continuous Read Mode with 8-clock address overhead. |
Use Scenario: Holding field-upgradable firmware images in medical diagnostic devices requiring safe dual-bank updates. IC Role / Device Role / Timing Role: Dual-image partitioning using 4KB sector granularity; isolated erase/write for atomic update rollback. Use Value: Sector-level erasure allows independent update of application vs. config partitions without disturbing boot code or calibration data. |
| Parameter & Calibration Data | Secure Key Storage |
|
Use Scenario: Retaining sensor calibration coefficients, motor tuning parameters, and user preferences in HVAC controllers. IC Role / Device Role / Timing Role: Low-power, long-retention non-volatile storage; accessed infrequently via Standard SPI during initialization. Use Value: Hardware write protection (/WP pin + BP bits) prevents accidental overwrite during runtime; 20-year retention ensures lifetime validity. |
Use Scenario: Storing AES keys and device-unique identifiers in payment terminal modules requiring FIPS-aligned security. IC Role / Device Role / Timing Role: Secure storage using OTP-locked Security Registers; accessed only during secure boot sequence. Use Value: Three 256-byte OTP registers prevent post-production modification; 64-bit Unique ID enables device binding and anti-cloning. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial NOR flash memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MX25L12833FZNI-10G | 128Mb density, 104MHz max clock, but lacks QPI mode and has no /RESET pin in 8-pin WSON; supports only Standard/Dual/Quad SPI | No QPI instruction set reduces instruction overhead savings; no dedicated reset function limits system-level recovery options | Select when QPI is unused and /RESET is handled externally; verify SFDP register compatibility for auto-configuration |
| S25FL128SAGMFI001 | 128Mb, 133MHz clock, supports HyperBus interface (not SPI/QPI); includes built-in ECC and configurable latency modes | HyperBus requires different controller IP and PCB layout; ECC adds reliability but increases complexity for simple storage use cases | Choose for high-speed parallel-like throughput in memory-mapped systems; avoid if existing design uses only SPI peripherals |
Compared with MX25L12833FZNI-10G and S25FL128SAGMFI001, W25Q128FVEIG TR uniquely balances QPI efficiency, integrated /HOLD–/RESET dual-function pin, and broad SPI mode compatibility - making it optimal for cost-sensitive, space-constrained designs needing flexible boot and update architectures without changing controller firmware.
Availability
W25Q128FVEIG TR is available at Aetrix Electronics and suitable for industrial control panels, IoT edge nodes, and consumer audio systems requiring stable component supply, extended temperature operation, and long-term firmware storage.
Supply support for W25Q128FVEIG TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Winbond Electronics is a Taiwan-based semiconductor company specializing in specialty DRAM, mobile DRAM, and serial flash memory solutions since 1987.
The W25Q series targets embedded systems requiring high-reliability, low-power, and multi-interface serial flash - designed specifically for boot code, firmware, and parameter storage in resource-constrained MCUs and SoCs.
FAQ
What interface protocols does the W25Q128FVEIG TR support?
The W25Q128FVEIG TR supports Standard SPI (4-wire), Dual I/O SPI, Quad I/O SPI, and Quad Peripheral Interface (QPI). QPI mode requires setting the Quad Enable (QE) bit in Status Register-2 and is enabled via the 38h instruction. In QPI mode, all instructions and data use 4-bit-wide transfers, reducing command overhead versus standard SPI.
Does the W25Q128FVEIG TR have a dedicated /RESET pin?
No - the W25Q128FVEIG TR does not include a dedicated /RESET pin in its 8-pin WSON 6×5-mm package. Instead, pin 7 functions as /HOLD or /RESET depending on the HOLD/RST bit in Status Register-3 and QE bit state. On 16-pin SOIC variants, a separate /RESET pin is provided, but W25Q128FVEIG TR uses the 8-pin WSON configuration.
How is hardware write protection implemented on the W25Q128FVEIG TR?
Hardware write protection on the W25Q128FVEIG TR combines the active-low /WP pin with non-volatile Block Protect (BP2–BP0), Top/Bottom (TB), Sector Protect (SEC), and Complement Protect (CMP) bits in the status register. When /WP is low and BP bits are set, corresponding 4KB sectors or larger blocks are locked against program/erase - independent of software commands.
What is the purpose of the SFDP register in the W25Q128FVEIG TR?
The SFDP (Serial Flash Discoverable Parameters) register (accessed via instruction 5Ah) provides standardized, vendor-agnostic timing, density, and feature information for automatic driver configuration. For W25Q128FVEIG TR, it reports erase times, voltage ranges, and supported instruction sets - enabling portable flash initialization across MCU platforms without hard-coded timing constants.
Can the W25Q128FVEIG TR be used for Execute-in-Place (XIP) applications?
Yes - the W25Q128FVEIG TR supports true XIP via Continuous Read Mode and Quad I/O or QPI interfaces. With as few as 8 clock cycles to address memory and up to 50 MB/s sustained read throughput, it delivers deterministic latency and bandwidth sufficient for direct code execution from flash in Cortex-M and RISC-V microcontrollers.
W25Q128FVEIG TR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Winbond Electronics Corporation
- Series:
- SpiFlash®
- Package/Case:
- 8-WDFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Discontinued at Digi-Key
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH - NOR
- Memory Size:
- 128Mbit
- Memory Organization:
- 16M x 8
- Memory Interface:
- SPI - Quad I/O, QPI
- Clock Frequency:
- 104 MHz
- Write Cycle Time - Word, Page:
- 50µs, 3ms
- Access Time:
- -
- Voltage - Supply:
- 2.7V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-WSON (8x6)
W25Q128FVEIG TR FAQ
1.How can I place an order for W25Q128FVEIG TR through Aetrix?
Please submit a Request for Quotation (RFQ) for W25Q128FVEIG TR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for W25Q128FVEIG TR reliable?
The price and inventory of W25Q128FVEIG TR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for W25Q128FVEIG TR is usually 5 days.
3.What payment methods are accepted for W25Q128FVEIG TR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for W25Q128FVEIG TR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for W25Q128FVEIG TR?
W25Q128FVEIG TR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your W25Q128FVEIG TR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for W25Q128FVEIG TR?
For technical support, including W25Q128FVEIG TR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your W25Q128FVEIG TR requirements.
6.How does Aetrix verify that W25Q128FVEIG TR is sourced from the original manufacturer or authorized distributors?
All W25Q128FVEIG TR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that W25Q128FVEIG TR meets industry standards.
7.What is the process for return or replacement of W25Q128FVEIG TR?
All W25Q128FVEIG TR units undergo pre-shipment inspection (PSI). If there is an issue with W25Q128FVEIG TR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The W25Q128FVEIG TR part is unused and in its original packaging.
Return procedure for W25Q128FVEIG TR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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