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Winbond Electronics Corporation W25Q128FVFIG TR
- Part No.:
- W25Q128FVFIG TR
- Manufacturer:
- Winbond Electronics Corporation
- Category:
- Memory
- Package:
- 16-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
W25Q128FVFIG TR.pdf
- Description:
- IC FLASH 128MBIT SPI/QUAD 16SOIC
- Quantity:
- Payment:
- Shipping:
Inventory:2,906
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Product details
Overview
W25Q128FVFIG TR from Winbond is a 3.3V, 128M-bit (16MB) serial NOR flash memory supporting Standard/Dual/Quad SPI and QPI interfaces. It features 4KB uniform sectors, 104MHz max clock frequency, 50MB/s continuous read throughput, and operates across –40°C to +85°C. It enables XIP (execute-in-place) code execution in embedded microcontrollers and stores firmware, configuration data, and boot images.
For engineers reviewing the W25Q128FVFIG TR datasheet, W25Q128FVFIG TR pinout, W25Q128FVFIG TR application, or W25Q128FVFIG TR equivalent, key selection criteria include Quad SPI enable (QE bit), /HOLD vs /RESET pin mapping per package, sector protection granularity, erase/program cycle endurance (>100k), and JEDEC SFDP register compatibility for auto-configuration.
Technical Context
The W25Q128FVFIG TR implements a flexible SPI-compatible command set with hardware- and software-controlled write protection, including top/bottom block lock, complement protection, and individual sector lock via dedicated instructions (36h/39h/3Dh). Its status registers support volatile/non-volatile configuration of QE, DRV0/DRV1 (output drive strength), HOLD/RST function selection, and security register locks.
It supports four operational modes: Standard SPI (4-wire), Dual I/O (5-wire), Quad I/O (6-wire), and QPI (6-wire with reduced instruction overhead). Mode switching requires explicit commands (38h to enter QPI, FFh to exit); Quad I/O mode requires QE=1 in Status Register-2, repurposing /WP and /HOLD as IO2 and IO3 respectively.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 128 M-bit (16 MB), organized as 65,536 × 256-byte pages |
| Supply Voltage | 2.7 V to 3.6 V - compatible with standard 3.3 V logic rails and LDO outputs |
| Max Clock Frequency | 104 MHz (SPI), enabling 208 MHz dual-I/O and 416 MHz quad-I/O effective throughput |
| Erase Granularity | Uniform 4 KB sectors (4,096 total), plus 32 KB and 64 KB blocks - supports fine-grained firmware partitioning |
| Endurance & Retention | 100,000 program/erase cycles; 20-year data retention at +85°C - suitable for field-upgradable systems |
| Interface Modes | Standard SPI, Dual I/O, Quad I/O, and QPI - selectable via instruction; QE bit controls IO2/IO3 remapping |
| Security Features | Three 256-byte OTP-lockable security registers, 64-bit unique ID, SFDP register, and programmable BP/TB/SEC bits |
Pinout & Package
W25Q128FVFIG TR uses an 8-pin SOIC 208-mil (Package Code S) with industry-standard pinout and 150 mil body width. Pin functions are shared across SPI modes: /CS selects device, CLK clocks data, DI/DO serve as unidirectional I/O in standard mode, and all four IOx pins operate bidirectionally in Quad mode when QE=1.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| /CS (Pin 1) | Chip Select Input | Active-low enable; high-impedance DO output and standby current when deasserted |
| DO / IO1 (Pin 2) | Data Output / Bidirectional I/O | Unidirectional output in standard SPI; bidirectional in Dual/Quad modes - requires pull-up for tri-state control |
| /WP / IO2 (Pin 3) | Write Protect Input / Bidirectional I/O | Hardware lock for status register when QE=0; becomes IO2 in Quad mode (QE=1) |
| GND (Pin 4) | Ground Reference | Primary return path for VCC and I/O signals; must be low-inductance for noise immunity |
| DI / IO0 (Pin 5) | Data Input / Bidirectional I/O | Unidirectional input in standard SPI; bidirectional in Dual/Quad modes - used for instruction/address/data ingress |
| CLK (Pin 6) | Serial Clock Input | Rising-edge sampled for input, falling-edge sampled for output - timing critical for >80 MHz operation |
| /HOLD or /RESET / IO3 (Pin 7) | Hold or Reset Input / Bidirectional I/O | Pauses ongoing SPI transfer when low (QE=0); becomes IO3 in Quad mode (QE=1); reset function only available on 16-pin SOIC or via software command |
| VCC (Pin 8) | Power Supply | 2.7–3.6 V supply; decoupling capacitor (100 nF) required within 5 mm of pin |
Key Features
| Feature | Design Value |
|---|---|
| Continuous Read Mode | As few as 8 clock cycles to initiate address fetch; enables true XIP without external cache or prefetch logic |
| Quad Peripheral Interface (QPI) | Reduces instruction overhead by encoding commands in 8-bit opcodes instead of 4-bit SPI opcodes - improves bus efficiency in high-throughput boot scenarios |
| Erase/Program Suspend & Resume | Allows background interrupt servicing during long erase operations (e.g., 64KB block erase ~200 ms) without data corruption |
| Individual Sector Lock | Per-sector (4KB) lock/unlock via 36h/39h instructions - isolates bootloader, parameter, and application partitions with hardware enforcement |
| JEDEC SFDP Register | Provides standardized, read-only parameter table (5Ah) for automatic driver initialization - eliminates hard-coded timing constants in BSPs |
Applications
| Industrial PLC Firmware Storage | Automotive ADAS Boot Image |
|---|---|
Use Scenario: Storing and executing real-time control firmware in programmable logic controllers with watchdog-timed updates. IC Role / Device Role / Timing Role: Nonvolatile code storage and XIP execution source; provides deterministic <100 ns access latency in QPI mode for critical task scheduling. Use Value: Eliminates external RAM copy step during boot; supports secure field updates via locked bootloader sector and SFDP-driven timing calibration. | Use Scenario: Holding certified boot firmware and sensor calibration data in automotive camera modules requiring AEC-Q100 compliance. IC Role / Device Role / Timing Role: Primary boot memory mapped to MCU's external memory interface; delivers 50 MB/s sustained read for fast cold-start (<500 ms). Use Value: Meets ASIL-B data integrity requirements via OTP-locked security registers and 20-year retention at +105°C derated operation. |
| Medical IoT Sensor Configuration | Consumer Router Web UI Assets |
Use Scenario: Persisting calibrated sensor offsets, patient history metadata, and regulatory audit logs in portable diagnostic devices. IC Role / Device Role / Timing Role: Parameter and data storage with hardware write protection; 4KB sector granularity enables independent update of calibration vs log regions. Use Value: Prevents accidental overwrite of FDA-cleared calibration data using /WP pin + BP bits; supports >100k reprogramming cycles for field recalibration. | Use Scenario: Hosting compressed HTML/CSS/JS assets and firmware images in Wi-Fi routers with limited PCB area. IC Role / Device Role / Timing Role: High-density code and asset storage; Quad SPI interface reduces pin count vs parallel NOR while maintaining >40 MB/s read speed. Use Value: Enables compact 8-pin SOIC footprint without sacrificing web UI load time; continuous read mode minimizes CPU wait states during asset streaming. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial NOR flash applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MX25L12833FZC-10G | 128Mb density, 104MHz max clock, same 8-pin SOIC package; supports DTR (double-transfer-rate) mode not present in W25Q128FVFIG TR | Requires DTR-capable controller; lacks QPI mode and SFDP register - limits auto-configuration capability | Select when DTR timing margin is needed and QPI/SFDP are unused; verify /HOLD pin behavior matches system hold timing budget |
| S25FL128SAGMFIR00 | 128Mb, 133MHz max clock, 8-pin SOIC; includes built-in ECC and configurable dummy cycles - no /RESET pin in 8-pin variant | Hardware ECC enables bit-error recovery in noisy environments; no dedicated /RESET pin requires software reset reliance | Prefer for mission-critical storage where single-bit error correction is mandated; confirm absence of /RESET does not impact system power-cycle robustness |
Compared with MX25L12833FZC-10G and S25FL128SAGMFIR00, the W25Q128FVFIG TR offers broader interface flexibility (QPI + SFDP) and integrated security registers, making it optimal for XIP-capable MCUs needing standardized configuration and firmware integrity - whereas alternatives prioritize raw speed or ECC at the cost of mode versatility.
Availability
W25Q128FVFIG TR is available at Aetrix Electronics and suitable for industrial control, automotive infotainment, medical diagnostics, and consumer networking applications requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant packaging.
Supply support for W25Q128FVFIG TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Winbond Electronics is a Taiwan-based semiconductor company specializing in specialty DRAM, mobile DRAM, and serial flash memory solutions for embedded, communications, and computing markets.
The W25Q series targets high-performance, space-constrained embedded systems requiring reliable code storage, XIP execution, and hardware-enforced security - with emphasis on interoperability across MCU platforms via JEDEC standards.
FAQ
What interface modes does the W25Q128FVFIG TR support, and how is Quad SPI enabled?
The W25Q128FVFIG TR supports Standard SPI, Dual I/O, Quad I/O, and QPI modes. Quad I/O mode is enabled by setting the Quad Enable (QE) bit in Status Register-2 using instruction 01h. When QE=1, the /WP and /HOLD pins become IO2 and IO3 respectively. The W25Q128FVFIG TR must be configured in this mode before issuing Quad-specific commands like 6Bh (Fast Read Quad Output) or 32h (Quad Input Page Program).
Does the W25Q128FVFIG TR include hardware reset functionality, and how is it implemented?
The W25Q128FVFIG TR supports hardware reset via the /RESET pin only in the 16-pin SOIC package (Package Code F). In the 8-pin SOIC package (W25Q128FVFIG TR), the Pin 7 function is configurable as either /HOLD or /RESET depending on the HOLD/RST bit in Status Register-3 - but this configuration is inactive when QE=1. For W25Q128FVFIG TR, software reset (66h + 99h) is the primary reset method; the /HOLD pin remains active for pause/resume control.
How does the W25Q128FVFIG TR handle write protection for critical firmware sectors?
The W25Q128FVFIG TR implements multi-layer write protection: hardware-level via the /WP pin (active-low, disables status register writes), and software-level via Block Protect (BP2–BP0), Top/Bottom (TB), Sector Protect (SEC), and Complement Protect (CMP) bits in Status Registers 1–3. These bits can lock individual 4KB sectors or contiguous blocks. The W25Q128FVFIG TR also supports individual sector lock/unlock using instructions 36h and 39h, enforced even when /WP is inactive.
What is the purpose of the SFDP register in the W25Q128FVFIG TR, and how is it accessed?
The SFDP (Serial Flash Discoverable Parameters) register in the W25Q128FVFIG TR is a standardized, read-only 256-byte table (accessed via instruction 5Ah) that describes device geometry, timing parameters, and feature support. It allows host drivers to auto-configure read latencies, dummy cycles, and voltage ranges without hard-coded values. The W25Q128FVFIG TR's SFDP complies with JEDEC JESD216B, enabling plug-and-play compatibility with modern MCU boot ROMs and flash programming tools.
Can the W25Q128FVFIG TR be used for execute-in-place (XIP) operation, and what conditions must be met?
Yes, the W25Q128FVFIG TR supports true XIP operation via Continuous Read Mode and QPI interface. To enable XIP, the host MCU must support memory-mapped SPI/QPI peripherals, the W25Q128FVFIG TR must be configured in QPI mode (38h), and the Continuous Read command (0Ch or 6Bh/EBh with wrap) must be issued first. The W25Q128FVFIG TR's 8-clock address setup and 416 MHz effective bandwidth ensure low-latency instruction fetches comparable to parallel NOR flash.
W25Q128FVFIG TR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Winbond Electronics Corporation
- Series:
- SpiFlash®
- Package/Case:
- 16-SOIC (0.295", 7.50mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Discontinued at Digi-Key
- Programmable:
- Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH - NOR
- Memory Size:
- 128Mbit
- Memory Organization:
- 16M x 8
- Memory Interface:
- SPI - Quad I/O, QPI
- Clock Frequency:
- 104 MHz
- Write Cycle Time - Word, Page:
- 50µs, 3ms
- Access Time:
- -
- Voltage - Supply:
- 2.7V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
W25Q128FVFIG TR FAQ
1.How can I place an order for W25Q128FVFIG TR through Aetrix?
Please submit a Request for Quotation (RFQ) for W25Q128FVFIG TR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for W25Q128FVFIG TR reliable?
The price and inventory of W25Q128FVFIG TR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for W25Q128FVFIG TR is usually 5 days.
3.What payment methods are accepted for W25Q128FVFIG TR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for W25Q128FVFIG TR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for W25Q128FVFIG TR?
W25Q128FVFIG TR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your W25Q128FVFIG TR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for W25Q128FVFIG TR?
For technical support, including W25Q128FVFIG TR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your W25Q128FVFIG TR requirements.
6.How does Aetrix verify that W25Q128FVFIG TR is sourced from the original manufacturer or authorized distributors?
All W25Q128FVFIG TR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that W25Q128FVFIG TR meets industry standards.
7.What is the process for return or replacement of W25Q128FVFIG TR?
All W25Q128FVFIG TR units undergo pre-shipment inspection (PSI). If there is an issue with W25Q128FVFIG TR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The W25Q128FVFIG TR part is unused and in its original packaging.
Return procedure for W25Q128FVFIG TR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
W25Q128FVFIG TR Tags
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