Winbond Electronics Corporation W25Q128FVFIQ TR
- Part No.:
- W25Q128FVFIQ TR
- Manufacturer:
- Winbond Electronics Corporation
- Category:
- Memory
- Package:
- 16-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
W25Q128FVFIQ TR.pdf
- Description:
- IC FLASH 128MBIT SPI/QUAD 16SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:4,570
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Product details
Overview
W25Q128FVFIQ TR from Winbond is a 3.3V, 128M-bit (16MB) serial NOR flash memory supporting Standard/Dual/Quad SPI and QPI interfaces. It delivers up to 104MHz clock rate (416MHz equivalent Quad I/O), 50MB/s continuous read throughput, and features uniform 4KB sectors, 256-byte page programming, and hardware write protection via /WP and /HOLD pins. It is used for code storage, XIP execution, firmware updates, and parameter logging in embedded microcontrollers and SoC boot systems.
For engineers reviewing the W25Q128FVFIQ TR datasheet, W25Q128FVFIQ TR pinout, W25Q128FVFIQ TR application, or W25Q128FVFIQ TR equivalent, key selection criteria include Quad SPI enable (QE bit), sector/block erase granularity, /RESET pin availability in 16-pin SOIC vs. /HOLD dual-function in 8-pin packages, and JEDEC ID/SFDP register support for automated configuration.
Technical Context
The W25Q128FVFIQ TR implements a flexible SPI-compatible command set with volatile/non-volatile status registers controlling Quad Enable (QE), Block Protect (BP2–BP0), Top/Bottom lock (TB), and Security Register locks (LB3–LB1). Its architecture supports concurrent erase/program suspend/resume, enabling background operations without halting host communication.
It operates across -40°C to +85°C with 2.7–3.6V supply, drawing 4mA active current and <1µA in power-down mode. The device integrates three 256-byte OTP-locked security registers, a 64-bit unique ID, and SFDP v1.6 compliance for automatic driver discovery - all accessible via standard SPI instructions like 9Fh (JEDEC ID) and 5Ah (SFDP read).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 128 M-bit (16 MB), organized as 65,536 × 256-byte pages |
| Interface Modes | Standard SPI (4-wire), Dual SPI (4-wire), Quad SPI (4-wire), QPI (6-wire); QE bit required for Quad I/O |
| Max Clock Rate | 104 MHz (SPI), enabling 208 MHz dual-I/O and 416 MHz quad-I/O effective bandwidth |
| Erase Granularity | Uniform 4 KB sectors (4,096 total), 32 KB blocks (256 total), 64 KB blocks (128 total), full-chip erase |
| Write Endurance | ≥100,000 program/erase cycles per sector |
| Data Retention | ≥20 years at +25°C; validated per JEDEC JESD22-A117 |
| Supply Voltage | 2.7 V to 3.6 V; compatible with 3.3 V logic families without level shifting |
| Operating Temp | -40°C to +85°C; qualified per AEC-Q100 Class 3 for industrial applications |
Pinout & Package
W25Q128FVFIQ TR uses an 8-pin WSON 6×5-mm package (Package Code P), with exposed pad for thermal dissipation. Pin 1 is /CS; pins 2–3 and 5–8 are bidirectional I/Os (IO0–IO3), /WP, /HOLD, CLK, and VCC/GND assigned per Figure 1b.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| /CS (Pin 1) | Chip Select Input | Active-low enable; high-impedance DO/IOx when deasserted; must transition high→low after power-up before first instruction |
| DO / IO1 (Pin 2) | Data Output / Quad I/O 1 | Unidirectional output in Standard SPI; bidirectional in Dual/Quad SPI/QPI; driven only when /CS low |
| /WP / IO2 (Pin 3) | Write Protect Input / Quad I/O 2 | Hardware lock for status register writes; disabled when QE=1 (becomes IO2) |
| GND (Pin 4) | Ground Reference | Primary return path; connects to PCB ground plane; critical for noise immunity in high-speed SPI |
| DI / IO0 (Pin 5) | Data Input / Quad I/O 0 | Unidirectional input in Standard SPI; bidirectional in Dual/Quad SPI/QPI; samples on CLK rising edge |
| CLK (Pin 6) | Serial Clock Input | Master-generated timing signal; defines data sampling (rising edge) and output (falling edge) windows |
| /HOLD / IO3 (Pin 7) | Hold Input / Quad I/O 3 | Pauses ongoing operation without deselecting; disabled when QE=1 (becomes IO3) |
| VCC (Pin 8) | Power Supply | 2.7–3.6 V supply; requires local 100 nF ceramic decoupling within 5 mm of pin |
Key Features
| Feature | Design Value |
|---|---|
| Quad Peripheral Interface (QPI) | Reduces instruction overhead to 2 clocks per byte; enables true XIP with continuous read wrap modes (8/16/32/64-byte) |
| Erase/Program Suspend & Resume | Allows host to pause background erase/program and service higher-priority reads/writes without data loss |
| Individual Sector Lock | Per-sector (4KB) software/hardware lock via 32h/39h/3Dh instructions; prevents accidental overwrite of critical firmware partitions |
| Security Registers | Three 256-byte OTP-locked registers (LB1–LB3) for storing cryptographic keys or calibration data inaccessible to standard read commands |
| SFDP v1.6 Compliance | Enables automatic driver initialization via 5Ah command; eliminates hardcoded timing parameters in bootloader code |
| Unique 64-bit ID | Factory-programmed serial number readable via 4Bh command; supports secure device authentication and traceability |
Applications
| IoT Edge Node Firmware Storage | Industrial PLC Boot Memory |
|---|---|
|
Use Scenario: Storing signed firmware images and OTA update payloads in battery-powered wireless sensors with constrained PCB area. IC Role / Device Role / Timing Role: Primary non-volatile code storage with Quad SPI XIP capability to reduce external RAM footprint and boot latency. Use Value: 4KB sector granularity enables atomic firmware swap; 1µA power-down current extends battery life; SFDP auto-configuration simplifies bootloader porting across sensor models. |
Use Scenario: Holding real-time OS kernel, configuration tables, and diagnostic logs in DIN-rail mounted programmable logic controllers. IC Role / Device Role / Timing Role: Boot ROM and runtime parameter store interfaced to ARM Cortex-M7 via QPI for deterministic 416 Mbps instruction fetch. Use Value: 100K-cycle endurance ensures reliable field updates over 10+ years; hardware /WP lock prevents corruption during brown-out events. |
| Automotive ADAS Camera Module | Medical Imaging Device Calibration Storage |
|
Use Scenario: Storing camera ISP firmware, lens correction profiles, and safety-critical boot code in ISO 26262-compliant vision ECUs. IC Role / Device Role / Timing Role: ASIL-B compliant code storage with dual-lock protection (SRP + TB bits) and ECC-enabled read verification. Use Value: 20-year data retention guarantees integrity across vehicle lifetime; /RESET pin (in SOIC-16 variant) enables fail-safe recovery independent of host MCU state. |
Use Scenario: Securing factory-calibrated gamma curves, sensor gain maps, and DICOM metadata in portable ultrasound units. IC Role / Device Role / Timing Role: Tamper-resistant parameter vault using OTP-locked security registers and individual sector locks. Use Value: 64-bit unique ID binds calibration data to specific hardware; 256-byte security registers prevent unauthorized reprogramming of medical settings. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial NOR flash memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MX25L12833FZNI-08G | 128Mb density, 133MHz max clock, no QPI mode, supports DTR (double-transfer-rate) but lacks SFDP v1.6 | Requires manual timing setup; no auto-discovery; suitable where QPI/XIP not needed and higher clock margin is critical | Select when prioritizing raw speed over configurability; verify /RESET pin presence matches board layout |
| S25FL128SAGMFI000 | 128Mb, 80MHz max clock, HyperBus interface option, integrated ECC, supports deep power-down mode (<100nA) | Lower active power but slower throughput; ECC enables uncorrectable-bit detection in safety-critical contexts | Prefer for ultra-low-power medical or aerospace use; avoid if Quad SPI/XIP boot path is fixed in existing design |
Compared with MX25L12833FZNI-08G and S25FL128SAGMFI000, the W25Q128FVFIQ TR uniquely balances QPI-based XIP performance, SFDP-driven flexibility, and industrial temperature reliability - making it optimal for resource-constrained embedded systems requiring both speed and configurability without redesigning the SPI controller stack.
Availability
W25Q128FVFIQ TR is available at Aetrix Electronics and suitable for IoT edge node firmware storage, industrial PLC boot memory, and automotive ADAS camera module applications requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant packaging.
Supply support for W25Q128FVFIQ TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Winbond Electronics is a Taiwan-based semiconductor company specializing in specialty DRAM, mobile DRAM, and serial flash memory solutions since 1987.
The W25Q series targets embedded systems needing high-speed, low-power, and secure code/data storage - designed specifically for XIP, OTA updates, and industrial-grade reliability without external voltage translators.
FAQ
What is the function of the /HOLD pin on the W25Q128FVFIQ TR?
The /HOLD pin on the W25Q128FVFIQ TR allows pausing ongoing SPI operations while maintaining chip select assertion. When pulled low during active communication, it places the DO/IOx lines in high-impedance state and ignores CLK/DI inputs. This enables time-sharing of SPI buses among multiple devices. Note that /HOLD is disabled when Quad Enable (QE) is set, as Pin 7 becomes IO3 in Quad SPI mode.
Does the W25Q128FVFIQ TR support execute-in-place (XIP) operation?
Yes, the W25Q128FVFIQ TR supports true XIP via its Continuous Read Mode and QPI interface. With as few as 8 clock cycles to address memory and wrap modes (8/16/32/64-byte), it delivers deterministic access latency suitable for direct code execution from flash. This eliminates need for external RAM loading in Cortex-M and RISC-V boot sequences.
How is hardware write protection implemented on the W25Q128FVFIQ TR?
Hardware write protection on the W25Q128FVFIQ TR uses the /WP pin in conjunction with status register bits (BP2–BP0, TB, SEC, CMP, SRP0/SRP1). When /WP is low, writes to protected sectors or the status register are blocked - even if software attempts them. Protection granularity ranges from single 4KB sectors to full array, and can be configured as top- or bottom-aligned.
What package type does the W25Q128FVFIQ TR use, and is thermal pad connected?
The W25Q128FVFIQ TR uses an 8-pin WSON 6×5-mm package (Package Code P) with an exposed thermal pad on the underside. The pad must be soldered to a PCB copper pour for thermal dissipation and mechanical stability. Electrical connection is not required, but grounding improves EMI performance and junction temperature margin during sustained read/write bursts.
Can the W25Q128FVFIQ TR be used in automotive applications?
The W25Q128FVFIQ TR is rated for -40°C to +85°C operation and meets industrial reliability standards, but it is not AEC-Q100 qualified. For automotive applications requiring ASIL-B compliance, Winbond offers the pin-compatible W25Q128JVSIM (AEC-Q100 Grade 3) - which shares identical electrical specs and command set but adds automotive qualification testing and extended temperature validation.
W25Q128FVFIQ TR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Winbond Electronics Corporation
- Series:
- SpiFlash®
- Package/Case:
- 16-SOIC (0.295", 7.50mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Discontinued at Digi-Key
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH - NOR
- Memory Size:
- 128Mbit
- Memory Organization:
- 16M x 8
- Memory Interface:
- SPI - Quad I/O, QPI
- Clock Frequency:
- 104 MHz
- Write Cycle Time - Word, Page:
- 50µs, 3ms
- Access Time:
- -
- Voltage - Supply:
- 2.7V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
W25Q128FVFIQ TR FAQ
1.How can I place an order for W25Q128FVFIQ TR through Aetrix?
Please submit a Request for Quotation (RFQ) for W25Q128FVFIQ TR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for W25Q128FVFIQ TR reliable?
The price and inventory of W25Q128FVFIQ TR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for W25Q128FVFIQ TR is usually 5 days.
3.What payment methods are accepted for W25Q128FVFIQ TR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for W25Q128FVFIQ TR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for W25Q128FVFIQ TR?
W25Q128FVFIQ TR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your W25Q128FVFIQ TR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for W25Q128FVFIQ TR?
For technical support, including W25Q128FVFIQ TR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your W25Q128FVFIQ TR requirements.
6.How does Aetrix verify that W25Q128FVFIQ TR is sourced from the original manufacturer or authorized distributors?
All W25Q128FVFIQ TR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that W25Q128FVFIQ TR meets industry standards.
7.What is the process for return or replacement of W25Q128FVFIQ TR?
All W25Q128FVFIQ TR units undergo pre-shipment inspection (PSI). If there is an issue with W25Q128FVFIQ TR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The W25Q128FVFIQ TR part is unused and in its original packaging.
Return procedure for W25Q128FVFIQ TR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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