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Winbond Electronics Corporation W25Q128FVFJP

Name: W25Q128FVFJP
Brand: Winbond Electronics Corporation
SKU: W25Q128FVFJP
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: W25Q128FVFJP

Manufacturer:: Winbond Electronics Corporation

Category:: Memory

Package:: 16-SOIC (0.295", 7.50mm Width)

Datasheet:: W25Q128FVFJP.pdf

Description:: IC FLASH 128MBIT SPI/QUAD 16SOIC

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Product details

Overview

W25Q128FVFJP from Winbond is a 3.3V, 128M-bit (16MB) serial NOR flash memory supporting Standard/Dual/Quad SPI and QPI interfaces. It features 4KB uniform sectors, 104MHz max clock frequency, 50MB/s continuous read throughput, and operates across –40°C to +85°C. It serves as nonvolatile code storage and XIP (execute-in-place) memory in microcontroller boot systems, IoT edge nodes, and industrial HMI displays.

For engineers reviewing the W25Q128FVFJP datasheet, W25Q128FVFJP pinout, W25Q128FVFJP application, or W25Q128FVFJP equivalent, key selection criteria include Quad SPI enable configuration (QE bit), /HOLD vs /RESET pin behavior per package, sector-level write protection granularity, and compatibility with legacy SPI controllers requiring /WP and /HOLD pins.

Technical Context

The W25Q128FVFJP implements a flexible multi-mode serial interface: Standard SPI uses DI/DO unidirectionally; Dual/Quad SPI repurpose /WP and /HOLD as IO2/IO3 when the non-volatile Quad Enable (QE) bit in Status Register-2 is set. QPI mode enables 4-bit instruction/data transfers with reduced command overhead, supporting true XIP operation via Continuous Read Mode with as few as 8 clocks for address setup.

Its memory array comprises 65,536 × 256-byte pages organized into 4,096 erasable 4KB sectors and 256 erasable 64KB blocks. Erase/program suspend-resume capability, volatile/non-volatile status register bits (BP2–BP0, TB, SEC, CMP, SRP0/SRP1), and three 256-byte OTP-lockable security registers provide robust data integrity control in field-deployed systems.

Key Specifications

Parameter	Value and Actual Design Meaning
Memory Density	128 M-bit (16 MB) - supports full firmware images for mid-tier MCUs without external memory expansion.
Interface Modes	Standard SPI, Dual SPI, Quad SPI, QPI - selectable via QE bit and instruction set; enables backward compatibility and bandwidth scaling.
Max Clock Frequency	104 MHz (SPI), 208 MHz equiv. (Dual I/O), 416 MHz equiv. (Quad I/O/QPI) - delivers 50 MB/s sustained read, outperforming parallel x16 Flash in pin-constrained designs.
Erase Granularity	4 KB sector / 32 KB block / 64 KB block / chip erase - allows fine-grained parameter updates without disturbing adjacent firmware sections.
Endurance & Retention	100,000 program/erase cycles, 20-year data retention - suitable for field-upgradable embedded devices with infrequent but critical writes.
Supply Voltage	2.7 V to 3.6 V - compatible with standard 3.3 V logic rails and brown-out tolerant power domains.
Operating Temp	–40°C to +85°C - qualified for industrial and automotive cabin applications without derating.

Pinout & Package

W25Q128FVFJP uses an 8-pin WSON 6×5-mm package (Package Code P), with exposed thermal pad. Pin functions are identical to SOIC/VSOP 208-mil: /CS, DO (IO1), /WP (IO2), GND, DI (IO0), CLK, /HOLD or /RESET (IO3), VCC.

Pin/Terminal	Circuit Role	Design Meaning
/CS	Chip Select Input	Active-low enable; high-impedance DO during deselect; required high→low transition after power-up before instruction acceptance.
DO (IO1)	Data Output / Bidirectional I/O	Unidirectional output in Standard SPI; bidirectional I/O in Dual/Quad modes; used for status/data reads on CLK falling edge.
/WP (IO2)	Write Protect Input / Bidirectional I/O	Hardware lock for status register writes when QE=0; becomes IO2 in Quad mode (QE=1); active-low, requires pull-up if unused.
GND	Ground Reference	Primary return path for VCC and I/O signals; must be low-inductance connection to minimize noise in high-speed SPI timing.
DI (IO0)	Data Input / Bidirectional I/O	Unidirectional input in Standard SPI; bidirectional I/O in Dual/Quad modes; accepts instructions/addresses/data on CLK rising edge.
CLK	Serial Clock Input	Master-generated timing reference; all I/O transitions synchronized to rising/falling edges per mode; max 104 MHz.
/HOLD or /RESET (IO3)	Hold Input / Reset Input / Bidirectional I/O	Pauses ongoing operations when low (/HOLD); resets internal state when pulsed (/RESET); becomes IO3 in Quad mode (QE=1).
VCC	Power Supply	2.7–3.6 V supply; decoupling capacitor (≥100 nF) required near pin; powers core, I/O, and charge pump for erase/program.

Key Features

Feature	Design Value
Continuous Read Mode	Enables XIP execution with ≤8-clock instruction overhead per 24-bit address fetch, eliminating need for external RAM buffering.
Quad Enable (QE) Bit	Non-volatile bit in Status Register-2 that permanently reassigns /WP and /HOLD to IO2/IO3 - required for Quad SPI/QPI operation.
Erase/Program Suspend	Allows temporary halt of long-duration erase/program cycles to service time-critical reads, resuming without data loss or timing penalty.
Individual Sector Lock	Per-sector write protection via 32-bit lock bits (36h/39h instructions), enabling secure firmware partitioning without global status register changes.
64-bit Unique ID	Factory-programmed, read-only serial number (4Bh instruction) - enables device authentication, secure boot binding, and field inventory tracking.

Applications

Industrial PLC Firmware Storage	Automotive Infotainment Boot Memory
Use Scenario: Storing bootloader and application firmware in programmable logic controllers with field update requirements and EMI-sensitive enclosures. IC Role / Device Role / Timing Role: Nonvolatile code storage with XIP support; provides deterministic 104MHz SPI access timing for real-time task scheduling. Use Value: 4KB sector erase enables incremental firmware patching without full reflash; 20-year retention ensures reliability over 15+ year product lifecycles.	Use Scenario: Hosting boot code and UI assets in head-unit systems where space, thermal budget, and ASIL-B compliance are critical. IC Role / Device Role / Timing Role: Primary boot memory interfaced to ARM Cortex-A MCU via Quad SPI; supports fast cold-start (<500ms) via Continuous Read Mode. Use Value: 50 MB/s read throughput reduces boot latency; unique ID enables secure firmware signing verification at power-on reset.
Medical Diagnostic Device Configuration	Smart Energy Meter Data Logging
Use Scenario: Storing calibration tables, patient safety parameters, and regulatory audit logs in portable ultrasound and ECG units. IC Role / Device Role / Timing Role: Parameter and event log storage with hardware write protection; uses /WP pin and BP bits for tamper-resistant configuration locking. Use Value: Individual sector lock (36h) prevents accidental overwrite of FDA-mandated calibration data; 100K-cycle endurance supports daily recalibration.	Use Scenario: Recording time-stamped energy consumption snapshots and tariff schedules in ANSI C12.22-compliant meters deployed in outdoor substations. IC Role / Device Role / Timing Role: Field-updatable nonvolatile data logger; leverages suspend/resume to avoid data loss during grid voltage dips. Use Value: –40°C to +85°C rating ensures operation in unheated meter cabinets; 4KB sectors align with ANSI C12.19 data record boundaries.

Industrial PLC Firmware Storage

Automotive Infotainment Boot Memory

Use Scenario: Storing bootloader and application firmware in programmable logic controllers with field update requirements and EMI-sensitive enclosures.

IC Role / Device Role / Timing Role: Nonvolatile code storage with XIP support; provides deterministic 104MHz SPI access timing for real-time task scheduling.

Use Value: 4KB sector erase enables incremental firmware patching without full reflash; 20-year retention ensures reliability over 15+ year product lifecycles.

Use Scenario: Hosting boot code and UI assets in head-unit systems where space, thermal budget, and ASIL-B compliance are critical.

IC Role / Device Role / Timing Role: Primary boot memory interfaced to ARM Cortex-A MCU via Quad SPI; supports fast cold-start (<500ms) via Continuous Read Mode.

Use Value: 50 MB/s read throughput reduces boot latency; unique ID enables secure firmware signing verification at power-on reset.

Medical Diagnostic Device Configuration

Smart Energy Meter Data Logging

Use Scenario: Storing calibration tables, patient safety parameters, and regulatory audit logs in portable ultrasound and ECG units.

IC Role / Device Role / Timing Role: Parameter and event log storage with hardware write protection; uses /WP pin and BP bits for tamper-resistant configuration locking.

Use Value: Individual sector lock (36h) prevents accidental overwrite of FDA-mandated calibration data; 100K-cycle endurance supports daily recalibration.

Use Scenario: Recording time-stamped energy consumption snapshots and tariff schedules in ANSI C12.22-compliant meters deployed in outdoor substations.

IC Role / Device Role / Timing Role: Field-updatable nonvolatile data logger; leverages suspend/resume to avoid data loss during grid voltage dips.

Use Value: –40°C to +85°C rating ensures operation in unheated meter cabinets; 4KB sectors align with ANSI C12.19 data record boundaries.

Equivalent & Alternatives

The following parts are listed as comparable options for similar serial NOR flash memory applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
MX25L12835FZNI-10G	128M-bit, 104MHz max, same 8-pin WSON 6×5-mm package; supports Standard/Dual/Quad SPI but no QPI mode; lacks /RESET pin function in 8-pin variant.	No QPI instruction set or Continuous Read Mode - limits XIP efficiency; no dedicated /RESET functionality in WSON package.	Select when QPI and hardware reset are unnecessary and cost sensitivity outweighs bandwidth flexibility.
S25FL128SAGMFI001	128M-bit, 133MHz max, 8-pin SOIC/WSON; includes HyperBus interface option; supports SFDP v1.6 but has different security register layout and no 64-bit UID.	HyperBus enables higher bandwidth than Quad SPI but requires controller-side IP licensing; different lock-bit mapping complicates migration.	Select when migrating from Cypress-based platforms or when HyperBus controller IP is already integrated and >50MB/s throughput is required.

Compared with MX25L12835FZNI-10G and S25FL128SAGMFI001, the W25Q128FVFJP uniquely combines QPI mode for minimal instruction overhead, factory-programmed 64-bit UID for secure boot, and /HOLD or /RESET dual-function pin in the compact WSON-8 package - making it optimal for new designs prioritizing XIP performance, traceability, and pin-count efficiency.

Availability

W25Q128FVFJP is available at Aetrix Electronics and suitable for industrial automation, automotive infotainment, and medical diagnostics requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant packaging.

Supply support for W25Q128FVFJP includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Winbond Electronics is a Taiwan-based semiconductor manufacturer specializing in specialty DRAM, mobile DRAM, and serial flash memory solutions since 1987.

The W25Q series targets embedded systems needing high-speed, low-pin-count nonvolatile storage; designed specifically for code execution, firmware updates, and secure parameter storage in resource-constrained environments.

FAQ

What interface modes does the W25Q128FVFJP support, and how is Quad SPI enabled?

The W25Q128FVFJP supports Standard SPI, Dual SPI, Quad SPI, and QPI. Quad SPI is enabled by setting the non-volatile Quad Enable (QE) bit in Status Register-2 using instruction 31h. When QE=1, the /WP and /HOLD pins become IO2 and IO3 respectively. This configuration is persistent across power cycles and must be verified before issuing Quad I/O commands like 6Bh (Fast Read Quad Output). The W25Q128FVFJP datasheet specifies that QE is non-volatile and survives power loss.

Does the W25Q128FVFJP have a dedicated /RESET pin, and how does it behave in the WSON-8 package?

The W25Q128FVFJP in WSON-8 package (FJP suffix) does not have a dedicated /RESET pin; instead, pin 7 functions as /HOLD or /RESET depending on the HOLD/RST bit (bit 7 of Status Register-3) and QE bit state. When QE=0, this pin operates as /HOLD; when QE=1, it becomes IO3 and /RESET is unavailable. Unlike the 16-pin SOIC variant, the WSON-8 package relies on software reset (66h/99h) or power cycle for reset functionality. This is explicitly defined in Section 3.3 and 4.6 of the W25Q128FVFJP datasheet.

How is write protection implemented on the W25Q128FVFJP, and what are the hardware options?

Write protection on the W25Q128FVFJP combines hardware and software methods: the /WP pin (active-low) locks Status Register writes when asserted, while BP2–BP0, TB, SEC, and CMP bits in Status Registers 1–3 define protected memory regions (4KB sectors up to full array). Hardware protection requires external pull-up/pull-down on /WP and proper VCC ramp tracking per Figure 58. The W25Q128FVFJP supports top/bottom array selection and complement protection, enabling asymmetric locking ideal for bootloader + application partitioning.

What is the purpose of the 64-bit Unique ID in the W25Q128FVFJP, and how is it accessed?

Each W25Q128FVFJP unit contains a factory-programmed, read-only 64-bit Unique ID used for device authentication, secure boot binding, and field inventory tracking. It is accessed via instruction 4Bh (Read Unique ID Number), requiring a 4-byte dummy address. The ID is stored in a one-time-programmable (OTP) region and cannot be modified. This feature is confirmed in Section 2 (Features) and Section 8.2.28 of the W25Q128FVFJP datasheet and is distinct from JEDEC ID (9Fh) or Manufacturer ID (90h).

Can the W25Q128FVFJP perform erase or program operations while servicing read requests?

Yes - the W25Q128FVFJP supports Erase/Program Suspend and Resume (instructions 75h and 7Ah). When suspended, it halts an ongoing erase or program cycle and immediately responds to read commands (e.g., 03h, 0Bh), then resumes the suspended operation upon resume command. This avoids data loss or timeout errors during time-critical reads in real-time systems. Suspend capability applies to sector/block/chip erase and page program operations, as specified in Sections 6.1.5 and 8.2.21–8.2.22 of the W25Q128FVFJP datasheet.

W25Q128FVFJP Specifications

Product attributes: Attribute value

Manufacturer:: Winbond Electronics Corporation

Series:: SpiFlash®

Package/Case:: 16-SOIC (0.295", 7.50mm Width)

Packaging:: Tube

Product Status:: Obsolete

Programmable:: Not Verified

Memory Type:: Non-Volatile

Memory Format:: FLASH

Technology:: FLASH - NOR

Memory Size:: 128Mbit

Memory Organization:: 16M x 8

Memory Interface:: SPI - Quad I/O, QPI

Clock Frequency:: 104 MHz

Write Cycle Time - Word, Page:: 50µs, 3ms

Access Time:: -

Voltage - Supply:: 2.7V ~ 3.6V

Operating Temperature:: -40°C ~ 105°C (TA)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 16-SOIC

W25Q128FVFJP FAQ

1.How can I place an order for W25Q128FVFJP through Aetrix?

Please submit a Request for Quotation (RFQ) for W25Q128FVFJP on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for W25Q128FVFJP reliable?

The price and inventory of W25Q128FVFJP are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for W25Q128FVFJP is usually 5 days.

3.What payment methods are accepted for W25Q128FVFJP?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for W25Q128FVFJP transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for W25Q128FVFJP?

W25Q128FVFJP orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your W25Q128FVFJP order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for W25Q128FVFJP?

For technical support, including W25Q128FVFJP datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your W25Q128FVFJP requirements.

6.How does Aetrix verify that W25Q128FVFJP is sourced from the original manufacturer or authorized distributors?

All W25Q128FVFJP products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that W25Q128FVFJP meets industry standards.

7.What is the process for return or replacement of W25Q128FVFJP?

All W25Q128FVFJP units undergo pre-shipment inspection (PSI). If there is an issue with W25Q128FVFJP, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The W25Q128FVFJP part is unused and in its original packaging.

Return procedure for W25Q128FVFJP:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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