Winbond Electronics Corporation W25Q128FVFJP TR
- Part No.:
- W25Q128FVFJP TR
- Manufacturer:
- Winbond Electronics Corporation
- Category:
- Memory
- Package:
- 16-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
W25Q128FVFJP TR.pdf
- Description:
- IC FLASH 128MBIT SPI/QUAD 16SOIC
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
W25Q128FVFJP TR from Winbond is a 128M-bit (16MB) serial NOR flash memory supporting Standard/Dual/Quad SPI and QPI interfaces, operating at 2.7–3.6V with 104MHz max clock, 4KB uniform sectors, and hardware write protection via /WP and /HOLD pins - used for code storage, XIP boot, and firmware updates in microcontroller-based embedded systems.
For engineers reviewing the W25Q128FVFJP TR datasheet, W25Q128FVFJP TR pinout, W25Q128FVFJP TR application, or W25Q128FVFJP TR equivalent, key selection considerations include Quad I/O enable (QE bit), 4KB sector erase granularity, JEDEC ID/SFDP register support, and compatibility with 8-pin SOIC-208mil footprint in space-constrained designs.
Technical Context
The W25Q128FVFJP TR implements a flexible SPI-compatible command set with volatile/non-volatile status registers controlling block protection (BP2–BP0), top/bottom lock (TB), security register locks (LB3–LB1), and quad enable (QE). Its architecture supports simultaneous read-while-write via Erase/Program Suspend/Resume functionality.
It delivers true execute-in-place (XIP) capability using Continuous Read Mode with ≤8-clock instruction overhead and wrap lengths of 8/16/32/64 bytes. QPI mode reduces instruction overhead by encoding commands and addresses in 4-bit nibbles per clock cycle, enabling 416MHz effective throughput with 104MHz CLK.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 128 M-bit (16 MB), organized as 65,536 × 256-byte pages |
| Interface Modes | Standard SPI, Dual I/O SPI, Quad I/O SPI, and Quad Peripheral Interface (QPI) |
| Max Clock Frequency | 104 MHz (supports 208 MHz dual-I/O and 416 MHz quad-I/O effective rates) |
| Erase Granularity | Uniform 4 KB sectors (4,096 total), plus 32 KB and 64 KB blocks |
| Write Endurance | 100,000 program/erase cycles per sector |
| Data Retention | 20 years at +25°C, verified per JEDEC JESD22-A117 |
| Operating Voltage | 2.7 V to 3.6 V single supply - compatible with 3.3 V logic systems |
| Power Consumption | 4 mA active current (typ.), <1 µA power-down current (typ.) |
Pinout & Package
W25Q128FVFJP TR uses an 8-pin SOIC-208mil package (Package Code S), with pin 1 = /CS, pin 2 = DO (IO1), pin 3 = /WP (IO2), pin 4 = GND, pin 5 = DI (IO0), pin 6 = CLK, pin 7 = /HOLD or /RESET (IO3), pin 8 = VCC. Pin 7 functions as /HOLD in standard/dual SPI mode; when QE=1, it becomes IO3 for quad operations.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| /CS (Pin 1) | Chip Select Input | Active-low enable: high = device deselected (high-Z outputs, standby current); low = device selected and responsive to commands |
| DO / IO1 (Pin 2) | Serial Data Output / Bidirectional I/O | Unidirectional output in standard SPI; bidirectional data lane 1 in dual/quad modes - enables full-duplex transfers |
| /WP / IO2 (Pin 3) | Hardware Write Protect / Bidirectional I/O | Active-low hardware lock for status register; repurposed as IO2 when QE=1 - disables hardware WP in quad mode |
| GND (Pin 4) | Ground Reference | Primary return path for VCC and all I/O signals; requires low-impedance PCB connection to minimize noise coupling |
| DI / IO0 (Pin 5) | Serial Data Input / Bidirectional I/O | Unidirectional input in standard SPI; bidirectional data lane 0 in dual/quad modes - carries commands, addresses, and data |
| CLK (Pin 6) | Serial Clock Input | Master-controlled timing reference for all SPI/QPI operations; rising edge samples inputs, falling edge drives outputs |
| /HOLD or /RESET / IO3 (Pin 7) | Hold Input or Reset Input / Bidirectional I/O | Pauses ongoing operation when low (with /CS low); dedicated reset on 16-pin variant; becomes IO3 when QE=1 |
| VCC (Pin 8) | Power Supply | 2.7–3.6 V supply with internal regulation - decoupling capacitor (≥100 nF) required within 1 cm of pin |
Key Features
| Feature | Design Value |
|---|---|
| Quad Peripheral Interface (QPI) | Reduces instruction overhead by encoding commands and addresses in 4-bit nibbles per clock, enabling deterministic 416 MHz effective bandwidth |
| Continuous Read Mode | Supports 8/16/32/64-byte wrap lengths with ≤8-clock address setup - eliminates per-byte command overhead for sequential access |
| Erase/Program Suspend & Resume | Allows background erase or program to be paused for urgent read operations, then resumed - critical for real-time firmware update scenarios |
| Security Registers | Three 256-byte OTP-lockable security registers for storing keys, certificates, or calibration data - protected by LB1–LB3 bits |
| SFDP Register Support | JEDEC JESD216-compliant Serial Flash Discoverable Parameters register - enables automatic driver configuration without hard-coded timing values |
| Unique 64-bit ID | Factory-programmed immutable serial number per die - used for device authentication, secure boot binding, and field traceability |
Applications
| IoT Edge Node Firmware Storage | Industrial PLC Boot Memory |
|---|---|
|
Use Scenario: Storing signed firmware images and OTA update payloads in battery-powered wireless sensors with constrained PCB area. IC Role / Device Role / Timing Role: Non-volatile code storage with XIP-capable Quad SPI interface for fast boot and low-power background updates. Use Value: 4KB sector erase enables atomic firmware patching; 1µA power-down current extends battery life between wake cycles. |
Use Scenario: Hosting bootloader and real-time control application code in DIN-rail mounted programmable logic controllers requiring high reliability. IC Role / Device Role / Timing Role: Primary boot memory mapped to MCU's external memory bus via Quad SPI, supporting deterministic startup under EMI-heavy factory environments. Use Value: 100,000 erase cycles and 20-year data retention ensure >10-year field service life without refresh; /WP pin prevents accidental corruption during brown-out events. |
| Medical Diagnostic Device Configuration | Automotive Infotainment HMI Storage |
|
Use Scenario: Storing calibrated sensor coefficients, user preferences, and regulatory compliance logs in portable ultrasound units. IC Role / Device Role / Timing Role: Parameter and data storage with hardware write protection (/WP) and individual sector locking (via 3Dh/36h instructions). Use Value: Security registers store cryptographic keys for HIPAA-compliant data encryption; SFDP register auto-configures timing for varying temperature conditions. |
Use Scenario: Holding GUI assets, voice prompts, and map tile caches in automotive head units where vibration and thermal cycling are extreme. IC Role / Device Role / Timing Role: High-bandwidth asset storage interfaced via QPI to reduce MCU load during graphics rendering and audio playback. Use Value: 416 MHz effective throughput sustains >50 MB/s continuous reads - sufficient for uncompressed 1080p video frame streaming from flash. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial NOR flash memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MX25L12833FZC-10G | 128 M-bit, 104 MHz max clock, SOIC-8 208-mil, but lacks QPI mode and SFDP register | No QPI support limits high-throughput use cases; no SFDP requires manual timing configuration in drivers | Choose when QPI and auto-discovery are unnecessary and cost sensitivity outweighs feature flexibility |
| S25FL128SAGMFI000 | 128 M-bit, 80 MHz max clock, SOIC-8 208-mil, includes HyperBus interface option and enhanced ECC | Lower bandwidth than W25Q128FVFJP TR; HyperBus adds pin count and controller complexity | Prefer when system already uses Cypress/Infineon HyperFlash ecosystem or requires built-in ECC for safety-critical logging |
Compared with MX25L12833FZC-10G and S25FL128SAGMFI000, the W25Q128FVFJP TR delivers higher effective throughput via QPI, deterministic XIP performance via Continuous Read Mode, and field-upgradable configuration via SFDP - making it optimal for new designs prioritizing software-defined timing and bandwidth scalability.
Availability
W25Q128FVFJP TR is available at Aetrix Electronics and suitable for IoT edge node firmware storage, industrial PLC boot memory, medical diagnostic device configuration, and automotive infotainment HMI storage requiring stable component supply across multi-year production cycles.
Supply support for W25Q128FVFJP TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Winbond Electronics is a Taiwan-based semiconductor company specializing in specialty DRAM, mobile DRAM, and serial flash memory solutions since 1987.
The W25Q series targets embedded systems requiring high-speed, low-power, and secure non-volatile storage - designed specifically for code execution, firmware updates, and parameter retention in resource-constrained MCUs.
FAQ
What is the package type and pin count of the W25Q128FVFJP TR?
The W25Q128FVFJP TR uses an 8-pin SOIC-208mil package (Package Code S), with standardized pinout including /CS, DO/IO1, /WP/IO2, GND, DI/IO0, CLK, /HOLD or /RESET/IO3, and VCC. This footprint is industry-standard and compatible with automated SMT assembly lines and legacy board layouts designed for similar serial flash devices.
Does the W25Q128FVFJP TR support execute-in-place (XIP) operation?
Yes, the W25Q128FVFJP TR supports true XIP via Continuous Read Mode with wrap lengths of 8/16/32/64 bytes and ≤8-clock instruction overhead. When paired with a QPI-capable host controller, it enables deterministic code fetch directly from flash without copying to RAM - reducing boot time and SRAM usage in Cortex-M and RISC-V microcontrollers.
How does hardware write protection work on the W25Q128FVFJP TR?
Hardware write protection on the W25Q128FVFJP TR is implemented via the active-low /WP pin, which - when asserted - prevents writes to the status register. It works in conjunction with non-volatile block protect bits (BP2–BP0), top/bottom lock (TB), and complement protect (CMP) to safeguard sectors as small as 4KB. Note that /WP is disabled when Quad Enable (QE) is set, as pin 3 becomes IO2.
What is the purpose of the /HOLD pin on the W25Q128FVFJP TR?
The /HOLD pin on the W25Q128FVFJP TR allows pausing ongoing SPI transactions while /CS remains low - placing DO in high-impedance state and ignoring DI/CLK edges. This enables bus sharing among multiple SPI slaves without requiring full deselect/reselect cycles. Like /WP, /HOLD is unavailable in Quad SPI mode (pin 7 becomes IO3 when QE=1).
Can the W25Q128FVFJP TR be used in automotive applications?
The W25Q128FVFJP TR is rated for –40°C to +85°C operation and meets industrial reliability standards (100,000 erase cycles, 20-year data retention), but it is not AEC-Q100 qualified. For non-safety-critical automotive infotainment or body-control modules operating within its temperature range, it is widely deployed - however, mission-critical ADAS or powertrain systems require AEC-Q100 Grade 2 or 3 qualified alternatives.
W25Q128FVFJP TR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Winbond Electronics Corporation
- Series:
- SpiFlash®
- Package/Case:
- 16-SOIC (0.295", 7.50mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH - NOR
- Memory Size:
- 128Mbit
- Memory Organization:
- 16M x 8
- Memory Interface:
- SPI - Quad I/O, QPI
- Clock Frequency:
- 104 MHz
- Write Cycle Time - Word, Page:
- 50µs, 3ms
- Access Time:
- -
- Voltage - Supply:
- 2.7V ~ 3.6V
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
W25Q128FVFJP TR FAQ
1.How can I place an order for W25Q128FVFJP TR through Aetrix?
Please submit a Request for Quotation (RFQ) for W25Q128FVFJP TR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for W25Q128FVFJP TR reliable?
The price and inventory of W25Q128FVFJP TR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for W25Q128FVFJP TR is usually 5 days.
3.What payment methods are accepted for W25Q128FVFJP TR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for W25Q128FVFJP TR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for W25Q128FVFJP TR?
W25Q128FVFJP TR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your W25Q128FVFJP TR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for W25Q128FVFJP TR?
For technical support, including W25Q128FVFJP TR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your W25Q128FVFJP TR requirements.
6.How does Aetrix verify that W25Q128FVFJP TR is sourced from the original manufacturer or authorized distributors?
All W25Q128FVFJP TR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that W25Q128FVFJP TR meets industry standards.
7.What is the process for return or replacement of W25Q128FVFJP TR?
All W25Q128FVFJP TR units undergo pre-shipment inspection (PSI). If there is an issue with W25Q128FVFJP TR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The W25Q128FVFJP TR part is unused and in its original packaging.
Return procedure for W25Q128FVFJP TR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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