My Inquiry
My Account
Winbond Electronics Corporation W25Q128FVPIQ TR
- Part No.:
- W25Q128FVPIQ TR
- Manufacturer:
- Winbond Electronics Corporation
- Category:
- Memory
- Package:
- 8-WDFN Exposed Pad
- Datasheet:
-
W25Q128FVPIQ TR.pdf
- Description:
- IC FLASH 128MBIT SPI/QUAD 8WSON
- Quantity:
- Payment:
- Shipping:
Inventory:2,276
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
W25Q128FVPIQ TR from Winbond is a 3.3V, 128M-bit (16MB) serial NOR flash memory supporting Standard/Dual/Quad SPI and QPI interfaces. It features 4KB uniform sectors, 104MHz max clock frequency, 50MB/s continuous read throughput, and operates from -40°C to +85°C. It serves as non-volatile code storage for microcontrollers in embedded boot applications requiring XIP execution or firmware parameter retention.
For engineers reviewing the W25Q128FVPIQ TR datasheet, W25Q128FVPIQ TR pinout, W25Q128FVPIQ TR application, or W25Q128FVPIQ TR equivalent, key selection criteria include Quad I/O enable (QE bit), /HOLD vs /RESET pin configuration per package, sector protection granularity, erase/program cycle endurance (>100k), and SFDP register support for auto-configuration.
Technical Context
The W25Q128FVPIQ TR implements a flexible SPI-compatible command set with hardware- and software-controlled write protection, including top/bottom block lock, complement protection, and individual sector lock via dedicated instructions (36h/39h/3Dh). Its status registers (SR1–SR3) provide volatile/non-volatile control of QE, BP bits, DRV strength, and HOLD/RST function mapping.
It supports true execute-in-place (XIP) operation via Continuous Read Mode (as few as 8 clocks to address memory) and QPI mode (38h entry, FFh exit), reducing instruction overhead versus standard SPI. Erase/program suspend/resume (75h/7Ah) enables concurrent background operations without halting host communication.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 128 M-bit (16 MB), organized as 65,536 × 256-byte pages |
| Interface Modes | Standard SPI, Dual I/O SPI, Quad I/O SPI, and Quad Peripheral Interface (QPI) |
| Max Clock Frequency | 104 MHz (SPI), enabling 208 MHz dual-I/O and 416 MHz quad-I/O effective rates |
| Erase Granularity | Uniform 4 KB sectors (4,096 total), 32 KB blocks (256 total), 64 KB blocks (128 total), full chip |
| Endurance & Retention | 100,000 program/erase cycles; 20-year data retention at +85°C |
| Supply Voltage | 2.7 V to 3.6 V; active current ≤4 mA, power-down current ≤1 µA (typ.) |
| Operating Temperature | -40°C to +85°C industrial grade |
| Security Features | 64-bit unique ID, three 256-byte OTP-lockable security registers, JEDEC SFDP register |
Pinout & Package
W25Q128FVPIQ TR is supplied in an 8-pin WSON 6×5-mm package (Package Code P), RoHS-compliant and lead-free. Pin 1 is /CS; Pin 2 is DO (IO1); Pin 3 is /WP (IO2); Pin 4 is GND; Pin 5 is DI (IO0); Pin 6 is CLK; Pin 7 is /HOLD or /RESET (IO3); Pin 8 is VCC. The /HOLD and /RESET functions are mutually exclusive and controlled by the HOLD/RST bit in Status Register-3.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| /CS (Pin 1) | Chip Select Input | Active-low enable; high-impedance output when deasserted; required low-to-high transition before first instruction post-power-up |
| DO / IO1 (Pin 2) | Data Output / Quad I/O Line 1 | Unidirectional output in Standard SPI; bidirectional I/O in Dual/Quad SPI/QPI modes |
| /WP / IO2 (Pin 3) | Write Protect Input / Quad I/O Line 2 | Hardware lock for status register when QE=0; becomes IO2 in Quad mode (QE=1) |
| GND (Pin 4) | Ground Reference | Primary return path for VCC and all I/O signals; must be low-impedance connection |
| DI / IO0 (Pin 5) | Data Input / Quad I/O Line 0 | Unidirectional input in Standard SPI; bidirectional I/O in Dual/Quad SPI/QPI modes |
| CLK (Pin 6) | Serial Clock Input | Edge-triggered timing reference for all SPI/QPI transfers; rising edge for input, falling edge for output |
| /HOLD or /RESET / IO3 (Pin 7) | Hold or Reset Input / Quad I/O Line 3 | Pauses ongoing operation when low (/HOLD); resets device state when pulsed (/RESET); becomes IO3 in Quad mode (QE=1) |
| VCC (Pin 8) | Power Supply | 2.7–3.6 V supply; decoupling capacitor (≥100 nF) required near pin for noise immunity |
Key Features
| Feature | Design Value |
|---|---|
| Quad Peripheral Interface (QPI) | Reduces instruction overhead via 4-bit-wide command/address/data transfers; enables deterministic latency for XIP |
| Continuous Read Mode | Supports wrap lengths of 8/16/32/64 bytes with only 8 clocks to initiate address transfer - critical for real-time code fetch |
| Erase/Program Suspend | Allows host to pause background erase or program operations (75h) and resume (7Ah) without data loss or timing violation |
| Flexible Protection Scheme | Combines hardware pins (/WP, /HOLD), volatile/non-volatile status bits (BP0–BP2, TB, SEC, CMP), and OTP-locked security registers |
| JEDEC SFDP Compliance | Enables automatic host configuration via standardized Serial Flash Discoverable Parameters register (5Ah) |
| Unique 64-bit ID | Factory-programmed per-device identifier used for secure firmware binding or anti-cloning in production systems |
Applications
| Industrial HMI Boot Storage | IoT Edge Device Firmware |
|---|---|
|
Use Scenario: Stores boot loader and GUI assets for ARM Cortex-M7-based human-machine interface panels operating in factory environments. IC Role / Device Role / Timing Role: Non-volatile code and asset storage with XIP-capable Quad SPI interface for deterministic startup and UI responsiveness. Use Value: 4KB sector erase enables over-the-air partial firmware updates without disrupting operational code sections. |
Use Scenario: Holds encrypted firmware images and calibration data for battery-powered smart sensors deployed in remote field locations. IC Role / Device Role / Timing Role: Secure, low-power persistent memory with OTP-locked security registers for cryptographic key isolation. Use Value: 1 µA power-down current extends battery life; 20-year data retention ensures calibration validity across product lifecycle. |
| Automotive Infotainment System | Medical Diagnostic Equipment |
|
Use Scenario: Stores audio codec firmware and user preference profiles in automotive head units compliant with AEC-Q100 Grade 3. IC Role / Device Role / Timing Role: High-reliability code storage with dual-power-supply lock-down and SRP-enabled status register protection. Use Value: 100,000 erase/program cycles support frequent firmware patches during vehicle service campaigns. |
Use Scenario: Retains FDA-mandated calibration logs and device-specific configuration parameters in portable ultrasound imaging modules. IC Role / Device Role / Timing Role: Tamper-resistant memory with 64-bit unique ID and SFDP-driven auto-configuration for regulatory traceability. Use Value: Security registers prevent unauthorized modification of diagnostic thresholds; JEDEC ID (9Fh) enables automated BOM verification. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial NOR flash memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MX25L12833FZC-10G | 128M-bit, 104MHz max clock, same 8-pin WSON 6×5-mm package; lacks QPI mode and SFDP register | No QPI or SFDP support limits auto-configuration capability; suitable for legacy SPI-only designs | Select when QPI/XIP is unnecessary and cost sensitivity outweighs configurability needs |
| S25FL128SAGMFI001 | 128M-bit, 80MHz max clock, 8-pin SOIC 208-mil; includes HyperBus interface option and enhanced ECC | Lower max frequency and SOIC packaging increase board area; HyperBus adds bandwidth but requires controller support | Prefer for systems needing built-in ECC for safety-critical data logging where timing margin allows 80MHz operation |
Compared with W25Q128FVPIQ TR, MX25L12833FZC-10G omits QPI and SFDP-reducing flexibility in modern MCU boot loaders-while S25FL128SAGMFI001 trades speed and package compactness for ECC robustness and alternate interface options, making it better suited for functional-safety contexts.
Availability
W25Q128FVPIQ TR is available at Aetrix Electronics and suitable for industrial HMI, IoT edge node, and medical diagnostic equipment requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant packaging.
Supply support for W25Q128FVPIQ TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Winbond Electronics is a Taiwan-based semiconductor manufacturer specializing in specialty memory solutions, including serial flash, RAM, and mobile DRAM, serving industrial, automotive, and consumer markets since 1987.
The W25Q series targets embedded systems requiring high-speed, low-power, and secure non-volatile storage-designed specifically for code shadowing, XIP execution, and firmware update resilience in resource-constrained environments.
FAQ
What is the package type and footprint compatibility of W25Q128FVPIQ TR?
W25Q128FVPIQ TR uses an 8-pin WSON 6×5-mm package (Package Code P) with exposed pad. It shares footprint compatibility with other Winbond WSON-8 variants like W25Q80DV and W25Q32JV, but pin functions differ due to /HOLD or /RESET mapping in Status Register-3. Always verify layout against the latest Winbond W25Q128FV datasheet Figure 1b and Table 3.3.
How does the Quad Enable (QE) bit affect pin functionality on W25Q128FVPIQ TR?
The QE bit (bit 1 of Status Register-2) controls whether pins 3 (/WP) and 7 (/HOLD or /RESET) operate as hardware control inputs or as Quad I/O lines IO2 and IO3. When QE=0, /WP and /HOLD are active; when QE=1, those pins become IO2 and IO3, disabling hardware write protect and hold functions. This setting is non-volatile unless cleared by Write Status Register-2 command.
Does W25Q128FVPIQ TR support execute-in-place (XIP) operation, and what conditions are required?
Yes, W25Q128FVPIQ TR supports true XIP via Continuous Read Mode and QPI. To enable XIP, the host MCU must support Quad I/O or QPI interface, the QE bit must be set, and the memory must be configured for wrap length (8/16/32/64 bytes) using instruction 77h. Fast Read Quad I/O (EBh) or QPI Read (03h in QPI mode) delivers deterministic latency essential for instruction fetch.
What write protection mechanisms are available on W25Q128FVPIQ TR?
W25Q128FVPIQ TR provides layered write protection: hardware pins (/WP active-low), volatile/non-volatile status register bits (BP0–BP2, TB, SEC, CMP), SRP bits to lock register writes, and OTP-locked security registers. Protection can be applied to top/bottom array halves, individual 4KB sectors, or the entire device-configurable via instructions 01h, 36h, 7Eh, and 42h.
Is W25Q128FVPIQ TR compatible with JEDEC-standard identification and configuration protocols?
Yes, W25Q128FVPIQ TR fully supports JEDEC standards: Manufacturer/Device ID (90h/9Fh), Unique ID (4Bh), and SFDP Register (5Ah). The SFDP table provides programmable parameters-including erase timings, voltage ranges, and Quad Enable behavior-enabling host firmware to auto-detect and configure the device without hard-coded assumptions.
W25Q128FVPIQ TR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Winbond Electronics Corporation
- Series:
- SpiFlash®
- Package/Case:
- 8-WDFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Discontinued at Digi-Key
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH - NOR
- Memory Size:
- 128Mbit
- Memory Organization:
- 16M x 8
- Memory Interface:
- SPI - Quad I/O, QPI
- Clock Frequency:
- 104 MHz
- Write Cycle Time - Word, Page:
- 50µs, 3ms
- Access Time:
- -
- Voltage - Supply:
- 2.7V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-WSON (6x5)
W25Q128FVPIQ TR FAQ
1.How can I place an order for W25Q128FVPIQ TR through Aetrix?
Please submit a Request for Quotation (RFQ) for W25Q128FVPIQ TR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for W25Q128FVPIQ TR reliable?
The price and inventory of W25Q128FVPIQ TR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for W25Q128FVPIQ TR is usually 5 days.
3.What payment methods are accepted for W25Q128FVPIQ TR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for W25Q128FVPIQ TR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for W25Q128FVPIQ TR?
W25Q128FVPIQ TR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your W25Q128FVPIQ TR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for W25Q128FVPIQ TR?
For technical support, including W25Q128FVPIQ TR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your W25Q128FVPIQ TR requirements.
6.How does Aetrix verify that W25Q128FVPIQ TR is sourced from the original manufacturer or authorized distributors?
All W25Q128FVPIQ TR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that W25Q128FVPIQ TR meets industry standards.
7.What is the process for return or replacement of W25Q128FVPIQ TR?
All W25Q128FVPIQ TR units undergo pre-shipment inspection (PSI). If there is an issue with W25Q128FVPIQ TR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The W25Q128FVPIQ TR part is unused and in its original packaging.
Return procedure for W25Q128FVPIQ TR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
W25Q128FVPIQ TR Tags
-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology
-
AT21CS01-STUM10-T
Microchip Technology
-
AT24C02C-SSHM-T
Microchip Technology
-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics
-
AT24CS02-SSHM-T
Microchip Technology
-
93LC46BT-I/OT
Microchip Technology
-
AT24C04C-SSHM-T
Microchip Technology
-
24LC01BT-I/SN
Microchip Technology
-
24AA02UIDT-I/OT
Microchip Technology
-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
