My Inquiry
My Account
Winbond Electronics Corporation W25Q128FVPJP
- Part No.:
- W25Q128FVPJP
- Manufacturer:
- Winbond Electronics Corporation
- Category:
- Memory
- Package:
- 8-WDFN Exposed Pad
- Datasheet:
-
W25Q128FVPJP.pdf
- Description:
- IC FLASH 128MBIT SPI/QUAD 8WSON
- Quantity:
- Payment:
- Shipping:
Inventory:2,455
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
W25Q128FVPJP from Winbond is a 128M-bit (16MB) serial NOR flash memory supporting Standard/Dual/Quad SPI and QPI interfaces, operating at 2.7–3.6V with 104MHz max clock, 4KB uniform sector erase, and 1µA power-down current. It enables XIP code execution in space-constrained embedded systems such as IoT edge nodes and industrial controllers.
For engineers reviewing the W25Q128FVPJP datasheet, W25Q128FVPJP pinout, W25Q128FVPJP application, or W25Q128FVPJP equivalent, key selection criteria include Quad I/O timing compliance, 4KB sector granularity for firmware partitioning, hardware write protection via /WP and /HOLD pins, and JEDEC SFDP register support for auto-configuration.
Technical Context
The W25Q128FVPJP implements a flexible SPI-compatible command set with volatile/non-volatile status registers controlling QE (Quad Enable), BP bits (sector/block protection), and HOLD/RST function mapping. Its architecture supports simultaneous read-while-erase/program suspend/resume operations and configurable output drive strength (DRV1/DRV0).
It delivers up to 50MB/s continuous read throughput using Fast Read Quad I/O (EBh) or QPI mode (38h), with instruction overhead reduced to just 8 clocks for address setup - enabling true execute-in-place (XIP) operation without external RAM buffering. The device uses a 65,536 × 256-byte page array organized into 4,096 sectors and 256 blocks.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 128 M-bit (16 MB), organized as 65,536 pages × 256 bytes |
| Interface Modes | Standard SPI, Dual I/O SPI, Quad I/O SPI, and QPI - all supported on same physical pins |
| Max Clock Frequency | 104 MHz (SPI); 208 MHz equivalent (Dual I/O); 416 MHz equivalent (Quad I/O/QPI) |
| Erase Granularity | Uniform 4 KB sectors (4,096 total), plus 32 KB and 64 KB block erase options |
| Write Endurance | 100,000 program/erase cycles per sector, ensuring long-term firmware update reliability |
| Data Retention | 20 years at +25°C, validated for industrial temperature range (-40°C to +85°C) |
| Power Supply | Single 2.7 V to 3.6 V supply; active current ≤4 mA, power-down current ≤1 µA (typ.) |
| Security Features | 64-bit unique ID, three 256-byte OTP-lockable security registers, SFDP register, and programmable BP/TB/SEC/CMP bits |
Pinout & Package
W25Q128FVPJP uses an 8-pin PDIP 300-mil package (Package Code A), with pin 1 = /CS, pin 2 = DO (IO1), pin 3 = /WP (IO2), pin 4 = GND, pin 5 = DI (IO0), pin 6 = CLK, pin 7 = /HOLD or /RESET (IO3), pin 8 = VCC. All I/O pins support bidirectional operation in Dual/Quad modes when QE=1.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| /CS (Pin 1) | Chip Select input | Active-low enable: high = high-Z outputs and standby current; low = active mode and instruction acceptance |
| DO / IO1 (Pin 2) | Data Output / Quad I/O line 1 | Unidirectional output in Standard SPI; bidirectional in Dual/Quad modes; used for status/data reads |
| /WP / IO2 (Pin 3) | Write Protect input / Quad I/O line 2 | Hardware lock for Status Register writes when QE=0; repurposed as IO2 in Quad mode (QE=1) |
| GND (Pin 4) | Ground reference | Primary return path for VCC and all I/O signals; must be low-impedance for timing integrity |
| DI / IO0 (Pin 5) | Data Input / Quad I/O line 0 | Unidirectional input in Standard SPI; bidirectional in Dual/Quad modes; carries instructions/addresses |
| CLK (Pin 6) | Serial clock input | Edge-triggered timing source for all SPI/QPI transfers; max 104 MHz; requires clean signal routing |
| /HOLD or /RESET (Pin 7) | Hold or Reset input / Quad I/O line 3 | Pauses ongoing transfers when low (HOLD); resets internal state when pulsed (RESET); becomes IO3 in Quad mode |
| VCC (Pin 8) | Power supply | 2.7–3.6 V single supply; decoupling capacitor required near pin for noise suppression |
Key Features
| Feature | Design Value |
|---|---|
| Quad Peripheral Interface (QPI) | Reduces instruction overhead to one 8-bit opcode per transaction, enabling deterministic XIP latency |
| Continuous Read Mode | Supports wrap lengths of 8/16/32/64 bytes with automatic address increment, eliminating repeated address sends |
| Erase/Program Suspend & Resume | Allows background read access during long erase/program operations - critical for real-time firmware updates |
| Flexible Hardware Write Protection | /WP pin + non-volatile BP/TB/SEC bits enable selective locking of boot sectors or configuration regions |
| JEDEC SFDP Register | Enables automatic driver initialization by host MCU without hard-coded timing or command tables |
| Unique 64-bit Serial Number | Provides immutable device identity for secure boot, anti-cloning, and field firmware traceability |
Applications
| Industrial PLC Firmware Storage | Automotive Infotainment Boot Code |
|---|---|
|
Use Scenario: Storing firmware images and configuration parameters in programmable logic controllers requiring field-upgradable code with data integrity guarantees. IC Role / Device Role / Timing Role: Non-volatile storage for boot loader, application firmware, and runtime parameter tables accessed via SPI during cold start and OTA updates. Use Value: 4KB sector erase enables atomic firmware patching without corrupting adjacent functional modules; 100K-cycle endurance supports >10 years of scheduled updates. |
Use Scenario: Hosting boot code and UI assets in automotive head units where AEC-Q100 qualification and fast XIP startup are mandatory. IC Role / Device Role / Timing Role: Primary boot memory mapped via Quad SPI to MCU's external memory interface, delivering sub-100ms cold-boot time. Use Value: 104MHz Quad I/O + Continuous Read achieves 416MB/s effective bandwidth, meeting ASAM boot timing requirements under -40°C to +85°C. |
| Medical Device Configuration Memory | Smart Meter Firmware & Calibration Data |
|
Use Scenario: Securely storing device-specific calibration coefficients, user preferences, and regulatory audit logs in Class II medical instruments. IC Role / Device Role / Timing Role: Trusted storage layer with hardware write protection and OTP-locked security registers preventing unauthorized reconfiguration. Use Value: Three 256-byte security registers with OTP locks ensure tamper-proof storage of FDA-required calibration signatures and revision history. |
Use Scenario: Holding firmware, tariff tables, and metrology calibration data in utility smart meters deployed in harsh outdoor environments. IC Role / Device Role / Timing Role: Long-life non-volatile memory interfaced to low-power MCU over SPI, surviving 20+ years with minimal maintenance. Use Value: 20-year data retention at +85°C and 1µA power-down current extend battery life in battery-backed meter designs. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial NOR flash applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MX25L12833FZC-10G | 128Mb density, 104MHz max clock, but only supports Standard/Dual SPI (no QPI or Quad I/O) | Lacks QPI mode and 416MHz equivalent bandwidth; no Continuous Read wrap support | Select when QPI/XIP is unnecessary and cost sensitivity outweighs performance needs |
| S25FL128SAGMFI000 | 128Mb, 133MHz, supports Octal DTR mode (not available on W25Q128FVPJP), includes built-in ECC | Higher bandwidth and error correction, but larger footprint (16-pin SOIC) and higher VCC min (2.7V vs 2.7V same) | Prefer for safety-critical applications requiring ECC and higher throughput; avoid if PCB space or legacy SPI-only host exists |
Compared with MX25L12833FZC-10G, W25Q128FVPJP delivers 4× faster effective read bandwidth via QPI and enables true XIP; versus S25FL128SAGMFI000, it trades ECC and Octal mode for smaller PDIP footprint and broader legacy SPI compatibility.
Availability
W25Q128FVPJP is available at Aetrix Electronics and suitable for industrial control systems, automotive infotainment modules, and medical instrumentation requiring stable component supply across extended product lifecycles.
Supply support for W25Q128FVPJP includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Winbond Electronics is a Taiwan-based semiconductor manufacturer specializing in specialty memory solutions, including SPI NOR/NAND flash and mobile DRAM.
The W25Q series targets embedded systems needing high-speed, low-power, and secure serial flash - designed specifically for code execution, firmware storage, and parameter retention in resource-constrained environments.
FAQ
What is the package type and pin count of the W25Q128FVPJP?
The W25Q128FVPJP uses an 8-pin PDIP (Plastic Dual In-line Package) with 300-mil body width (Package Code A). Pin assignments are /CS (1), DO/IO1 (2), /WP/IO2 (3), GND (4), DI/IO0 (5), CLK (6), /HOLD or /RESET/IO3 (7), and VCC (8). This through-hole package supports manual soldering and prototyping while maintaining full electrical compatibility with surface-mount variants of the W25Q128FV family.
Does the W25Q128FVPJP support Quad SPI and QPI modes?
Yes, the W25Q128FVPJP supports both Quad SPI and QPI modes. Quad SPI operation requires setting the Quad Enable (QE) bit in Status Register-2, which repurposes the /WP and /HOLD pins as IO2 and IO3. QPI mode is entered using the 0x38 instruction and provides single-cycle opcode addressing, reducing protocol overhead significantly compared to standard SPI - a capability confirmed in the official Winbond datasheet Revision M.
What is the minimum and maximum supply voltage for reliable operation of the W25Q128FVPJP?
The W25Q128FVPJP operates reliably across a supply voltage range of 2.7 V to 3.6 V. Operation below 2.7 V may cause undefined behavior or failure to accept commands; above 3.6 V risks permanent damage. The device draws ≤4 mA during active read/write and as low as 1 µA in power-down mode - making it suitable for battery-powered applications where supply regulation stability is critical for W25Q128FVPJP functionality.
How many program/erase cycles does the W25Q128FVPJP guarantee?
The W25Q128FVPJP guarantees a minimum of 100,000 program/erase cycles per sector. This endurance rating applies uniformly across all 4,096 sectors and is validated under standard industrial conditions (25°C, VCC = 3.0 V). Combined with 20-year data retention, this ensures robust support for frequent firmware updates in devices like smart meters and industrial gateways where W25Q128FVPJP serves as primary non-volatile storage.
Can the W25Q128FVPJP be used for execute-in-place (XIP) applications?
Yes, the W25Q128FVPJP supports true execute-in-place (XIP) operation via its Continuous Read Mode and QPI interface. With as few as 8 clock cycles needed to initiate a read and support for 8/16/32/64-byte wrap, it enables deterministic, low-latency instruction fetch directly from flash - eliminating the need for RAM shadowing in microcontrollers with external memory buses. This XIP capability is explicitly documented for W25Q128FVPJP in Section 1 and Figure 2 of the datasheet.
W25Q128FVPJP Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Winbond Electronics Corporation
- Series:
- SpiFlash®
- Package/Case:
- 8-WDFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH - NOR
- Memory Size:
- 128Mbit
- Memory Organization:
- 16M x 8
- Memory Interface:
- SPI - Quad I/O, QPI
- Clock Frequency:
- 104 MHz
- Write Cycle Time - Word, Page:
- 50µs, 3ms
- Access Time:
- -
- Voltage - Supply:
- 2.7V ~ 3.6V
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-WSON (6x5)
W25Q128FVPJP FAQ
1.How can I place an order for W25Q128FVPJP through Aetrix?
Please submit a Request for Quotation (RFQ) for W25Q128FVPJP on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for W25Q128FVPJP reliable?
The price and inventory of W25Q128FVPJP are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for W25Q128FVPJP is usually 5 days.
3.What payment methods are accepted for W25Q128FVPJP?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for W25Q128FVPJP transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for W25Q128FVPJP?
W25Q128FVPJP orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your W25Q128FVPJP order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for W25Q128FVPJP?
For technical support, including W25Q128FVPJP datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your W25Q128FVPJP requirements.
6.How does Aetrix verify that W25Q128FVPJP is sourced from the original manufacturer or authorized distributors?
All W25Q128FVPJP products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that W25Q128FVPJP meets industry standards.
7.What is the process for return or replacement of W25Q128FVPJP?
All W25Q128FVPJP units undergo pre-shipment inspection (PSI). If there is an issue with W25Q128FVPJP, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The W25Q128FVPJP part is unused and in its original packaging.
Return procedure for W25Q128FVPJP:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
W25Q128FVPJP Tags
-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology
-
AT21CS01-STUM10-T
Microchip Technology
-
AT24C02C-SSHM-T
Microchip Technology
-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics
-
AT24CS02-SSHM-T
Microchip Technology
-
93LC46BT-I/OT
Microchip Technology
-
AT24C04C-SSHM-T
Microchip Technology
-
24LC01BT-I/SN
Microchip Technology
-
24AA02UIDT-I/OT
Microchip Technology
-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
