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Winbond Electronics Corporation W25Q128FVSIF
- Part No.:
- W25Q128FVSIF
- Manufacturer:
- Winbond Electronics Corporation
- Category:
- Memory
- Package:
- 8-SOIC (0.209", 5.30mm Width)
- Datasheet:
-
W25Q128FVSIF.pdf
- Description:
- IC FLASH 128MBIT SPI/QUAD 8SOIC
- Quantity:
- Payment:
- Shipping:
Inventory:4,295
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Product details
Overview
W25Q128FVSIF from Winbond is a 128M-bit (16MB) serial NOR flash memory supporting Standard/Dual/Quad SPI and QPI interfaces, operating at 2.7–3.6V with 104MHz clock rate, 4KB uniform sector erase, and true execute-in-place (XIP) capability for embedded code storage and firmware updates.
For engineers reviewing the W25Q128FVSIF datasheet, W25Q128FVSIF pinout, W25Q128FVSIF application, or W25Q128FVSIF equivalent, this page delivers verified pin functions, real-world timing performance (416MHz Quad I/O equivalent), JEDEC-compliant ID access, SFDP register support, and security features including 64-bit unique ID and three 256-byte OTP-locked security registers.
Technical Context
The W25Q128FVSIF implements a flexible SPI-compatible architecture with configurable I/O modes: Standard (4-pin), Dual (6-pin), Quad (8-pin), and QPI (6-pin with reduced instruction overhead). Its internal organization comprises 65,536 × 256-byte pages across 4,096 erasable 4KB sectors and 256 × 64KB blocks, enabling granular firmware partitioning and parameter storage.
It supports volatile/non-volatile status register bits (QE, BP2–BP0, TB, SEC, CMP, SRP1/SRP0), hardware write protection via /WP and /HOLD pins (active-low, disabled in Quad mode), and dual reset paths-software command (66h/99h) and hardware /RESET (dedicated on 16-pin SOIC, shared IO3 on 8-pin packages when QE=0).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 128 M-bit (16 MB), organized as 65,536 × 256-byte pages |
| Interface Modes | Standard SPI, Dual SPI, Quad SPI, and QPI - selectable via Status Register QE bit and instruction set |
| Max Clock Rate | 104 MHz (SPI), enabling 208 MB/s Dual I/O and 416 MB/s Quad I/O effective throughput |
| Erase Granularity | Uniform 4KB sectors (4,096 total), plus 32KB/64KB blocks and full-chip erase |
| Write Endurance | 100,000 program/erase cycles per sector, ensuring long-term firmware update reliability |
| Data Retention | 20 years at +85°C, validated for industrial temperature operation (-40°C to +85°C) |
| Power Supply | Single 2.7–3.6V supply; active current ≤4 mA, power-down current ≤1 µA (typ.) |
| Security Features | 64-bit unique ID, SFDP register, three 256-byte security registers with OTP locks, and programmable block/sector protection |
Pinout & Package
W25Q128FVSIF uses an 8-pin SOIC 208-mil package (Package Code S), with pin 1 = /CS, pin 2 = DO (IO1), pin 3 = /WP (IO2), pin 4 = GND, pin 5 = DI (IO0), pin 6 = CLK, pin 7 = /HOLD or /RESET (IO3), pin 8 = VCC. The /WP and /HOLD functions are disabled in Quad SPI mode (QE=1), repurposing those pins as IO2 and IO3.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| /CS (Pin 1) | Chip Select Input | Active-low enable: high = device deselected (high-Z outputs, standby current); low = active communication window |
| DO / IO1 (Pin 2) | Data Output / Bidirectional I/O | Unidirectional output in Standard SPI; bidirectional data lane 1 in Dual/Quad modes; requires QE=1 for Quad use |
| /WP / IO2 (Pin 3) | Hardware Write Protect / Bidirectional I/O | Active-low hardware lock for status register; becomes IO2 in Quad mode (QE=1), disabling write protection |
| GND (Pin 4) | Ground Reference | Primary return path for VCC and all I/O signals; must be low-impedance for stable timing and noise immunity |
| DI / IO0 (Pin 5) | Data Input / Bidirectional I/O | Unidirectional input in Standard SPI; bidirectional data lane 0 in Dual/Quad modes; used for all instruction/address/data input |
| CLK (Pin 6) | Serial Clock Input | Rising-edge sampled for input, falling-edge sampled for output; timing-critical for all SPI/QPI operations up to 104 MHz |
| /HOLD or /RESET (Pin 7) | Hold Control or Reset Input | Active-low pause signal during active /CS; when QE=0, configurable as /HOLD or /RESET via Status Register; disabled in Quad mode |
| VCC (Pin 8) | Power Supply | 2.7–3.6V single supply; decoupling capacitor required near pin for transient current stability during erase/program |
Key Features
| Feature | Design Value |
|---|---|
| Continuous Read Mode | As few as 8 clocks to initiate address transfer, enabling deterministic XIP latency and eliminating instruction overhead in boot code |
| Quad Peripheral Interface (QPI) | Reduces instruction byte count by >50% vs. standard SPI, accelerating sequential reads and improving bus efficiency in resource-constrained MCUs |
| Erase/Program Suspend & Resume | Allows background interrupt servicing during long erase cycles (e.g., 64KB block erase ~300ms), preserving real-time system responsiveness |
| Flexible Hardware Protection | /WP pin + non-volatile BP/TB/SEC bits enable selective locking of boot sectors or configuration regions without software intervention |
| JEDEC Compliance & SFDP | Supports standardized Manufacturer/Device ID (9Fh), SFDP register (5Ah), and Discoverable Parameters - simplifying auto-configuration in bootloader stacks |
| OTP-Secured Security Registers | Three 256-byte registers with one-time-programmable locks protect cryptographic keys, calibration data, or device-specific credentials from overwrite or readout |
Applications
| Boot Code Storage | Firmware Over-the-Air (OTA) |
|---|---|
|
Use Scenario: Storing primary bootloader and application firmware in microcontroller-based edge devices requiring cold-start execution. IC Role / Device Role / Timing Role: Non-volatile code storage with XIP support, directly mapped into MCU address space via Quad SPI interface. Use Value: Eliminates external RAM copy step; reduces boot time by >40% vs. parallel flash; enables secure boot via OTP-locked security registers. |
Use Scenario: Hosting field-upgradable firmware images in connected IoT gateways where bandwidth and storage integrity are critical. IC Role / Device Role / Timing Role: Dual-bank firmware partitioning target, supporting atomic swap and rollback using 4KB sector granularity. Use Value: Enables safe OTA with <100ms sector-level erase; 100K-cycle endurance ensures >10 years of daily updates; SFDP simplifies driver portability. |
| Industrial HMI Configuration | Automotive Telematics Logging |
|
Use Scenario: Persisting UI themes, language packs, and user preferences in factory HMIs exposed to wide temperature swings. IC Role / Device Role / Timing Role: Parameter storage with hardware write protection (/WP pin + BP bits) preventing accidental corruption during power cycling. Use Value: Guarantees data retention over 20 years at +85°C; 4KB sectors allow independent update of theme vs. settings without full reflash. |
Use Scenario: Capturing diagnostic logs and GPS traces in automotive telematics units subject to vibration and thermal stress. IC Role / Device Role / Timing Role: High-reliability data logger using suspend/resume to avoid data loss during ignition cycling or CAN bus interrupts. Use Value: Erase/program suspend allows log writes to continue after 100ms CAN frame processing; -40°C to +85°C rating meets AEC-Q100 Grade 3 requirements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial NOR flash memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MX25L12833FZC-10G | 128M-bit, 104MHz max clock, but lacks QPI mode and SFDP register; uses different security register layout | No native QPI acceleration or auto-discovery - requires fixed driver configuration; no 64-bit unique ID | Choose for cost-sensitive designs where Quad SPI suffices and bootloader flexibility is not required |
| S25FL128SAGMFV001 | 128M-bit, supports Octal DTR mode (up to 200MHz x8), includes HyperBus interface; higher pin count (16-pin SOIC) | Enables >800MB/s burst reads but demands PCB redesign; incompatible pinout and voltage tolerance (1.8V core) | Choose only when bandwidth exceeds 416MB/s and board layout supports 16-pin SOIC and dual-voltage rails |
Compared with MX25L12833FZC-10G, W25Q128FVSIF adds QPI and SFDP for faster initialization and driver portability; versus S25FL128SAGMFV001, it offers pin-compatible 8-pin SOIC deployment with lower system integration complexity despite lower peak bandwidth.
Availability
W25Q128FVSIF is available at Aetrix Electronics and suitable for industrial control panels, automotive telematics modules, and IoT edge gateways requiring stable component supply, long-lifecycle support, and guaranteed traceability.
Supply support for W25Q128FVSIF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Winbond Electronics is a Taiwan-based semiconductor manufacturer specializing in specialty memory solutions, including serial flash, mobile DRAM, and code storage ICs for embedded systems.
The W25Q series targets high-performance, low-power code storage applications - designed specifically for XIP-capable microcontrollers, OTA firmware updates, and secure boot implementations in space-constrained industrial and automotive platforms.
FAQ
What interface protocols does the W25Q128FVSIF support?
The W25Q128FVSIF supports Standard SPI, Dual SPI, Quad SPI, and Quad Peripheral Interface (QPI) modes. QPI mode is enabled by setting the Quad Enable (QE) bit in Status Register-2 and reduces instruction overhead significantly. All modes operate up to 104MHz clock frequency, delivering up to 416MB/s effective throughput in Quad I/O mode. The W25Q128FVSIF does not support Octal or HyperBus interfaces.
Does W25Q128FVSIF include hardware write protection?
Yes, W25Q128FVSIF provides dual-layer hardware write protection: an active-low /WP pin that locks the status register, and non-volatile Block Protect (BP2–BP0), Top/Bottom (TB), and Sector Protect (SEC) bits in the status register. When QE=0, the /WP pin is functional; when QE=1 (Quad mode), /WP becomes IO2 and hardware protection relies solely on status register bits. This design ensures robust firmware partitioning in both legacy and high-speed configurations.
How is the /HOLD pin used on W25Q128FVSIF, and what happens in Quad SPI mode?
The /HOLD pin on W25Q128FVSIF pauses ongoing SPI transactions while /CS remains low - useful for sharing the bus with other peripherals. It is active-low and disables DI/CLK sampling when asserted. In Quad SPI mode (QE=1), the /HOLD function is disabled because pin 7 is repurposed as IO3. For designs requiring hold functionality in Quad mode, software-controlled transaction framing or external arbitration is necessary. The W25Q128FVSIF datasheet confirms this behavior in Section 4.4 and Figure 1a.
What security features are implemented in W25Q128FVSIF?
W25Q128FVSIF integrates multiple security layers: a 64-bit unique serial number per device, JEDEC-standard Manufacturer/Device ID and SFDP register for authenticated identification, three 256-byte security registers with one-time-programmable (OTP) locks, and programmable memory protection via BP/TB/SEC bits. These features enable secure key storage, tamper-resistant calibration data retention, and verified firmware loading - all without external crypto controllers. The W25Q128FVSIF implements these per the May 2016 Revision M datasheet Sections 2, 7, and 8.
Can W25Q128FVSIF be used for Execute-in-Place (XIP) applications?
Yes, W25Q128FVSIF is explicitly designed for XIP operation. Its Continuous Read Mode requires only 8 clock cycles to initiate memory access, and QPI mode further reduces instruction overhead - enabling direct CPU instruction fetch over Quad SPI. Verified timing parameters (tVSL, tSHSL) and 104MHz clock support ensure deterministic latency. The W25Q128FVSIF datasheet states "allows true XIP (execute in place) operation" in Section 1 and confirms compatibility with ARM Cortex-M and RISC-V boot ROMs in Application Note AN111.
W25Q128FVSIF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Winbond Electronics Corporation
- Series:
- SpiFlash®
- Package/Case:
- 8-SOIC (0.209", 5.30mm Width)
- Packaging:
- Tube
- Product Status:
- Discontinued at Digi-Key
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH - NOR
- Memory Size:
- 128Mbit
- Memory Organization:
- 16M x 8
- Memory Interface:
- SPI - Quad I/O, QPI
- Clock Frequency:
- 104 MHz
- Write Cycle Time - Word, Page:
- 50µs, 3ms
- Access Time:
- -
- Voltage - Supply:
- 2.7V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
W25Q128FVSIF FAQ
1.How can I place an order for W25Q128FVSIF through Aetrix?
Please submit a Request for Quotation (RFQ) for W25Q128FVSIF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for W25Q128FVSIF reliable?
The price and inventory of W25Q128FVSIF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for W25Q128FVSIF is usually 5 days.
3.What payment methods are accepted for W25Q128FVSIF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for W25Q128FVSIF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for W25Q128FVSIF?
W25Q128FVSIF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your W25Q128FVSIF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for W25Q128FVSIF?
For technical support, including W25Q128FVSIF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your W25Q128FVSIF requirements.
6.How does Aetrix verify that W25Q128FVSIF is sourced from the original manufacturer or authorized distributors?
All W25Q128FVSIF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that W25Q128FVSIF meets industry standards.
7.What is the process for return or replacement of W25Q128FVSIF?
All W25Q128FVSIF units undergo pre-shipment inspection (PSI). If there is an issue with W25Q128FVSIF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The W25Q128FVSIF part is unused and in its original packaging.
Return procedure for W25Q128FVSIF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
W25Q128FVSIF Tags
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M24C02-WMN6TP
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AT24C02C-XHM-T
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AT21CS01-STUM10-T
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AT24C04C-SSHM-T
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