My Inquiry
My Account
Winbond Electronics Corporation W25Q128FVSIG
- Part No.:
- W25Q128FVSIG
- Manufacturer:
- Winbond Electronics Corporation
- Category:
- Memory
- Package:
- 8-SOIC (0.209", 5.30mm Width)
- Datasheet:
-
W25Q128FVSIG.pdf
- Description:
- IC FLASH 128MBIT SPI/QUAD 8SOIC
- Quantity:
- Payment:
- Shipping:
Inventory:1,998
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
W25Q128FVSIG from Winbond is a 3.3V, 128M-bit (16MB) serial NOR flash memory supporting Standard/Dual/Quad SPI and QPI interfaces. It delivers up to 104MHz clock rate (416MHz equivalent Quad I/O), 50MB/s continuous read throughput, and features uniform 4KB sectors, 32KB/64KB blocks, and chip erase. It is used for code execution in place (XIP), firmware storage, and parameter retention in microcontroller-based embedded systems.
For engineers reviewing the W25Q128FVSIG datasheet, W25Q128FVSIG pinout, W25Q128FVSIG application, or W25Q128FVSIG equivalent, key selection criteria include Quad Enable (QE) bit configuration, /HOLD vs /RESET pin behavior per package, sector protection granularity, SFDP register support, and power-down current (<1µA typical).
Technical Context
The W25Q128FVSIG implements a flexible SPI-compatible command set with hardware- and software-controlled write protection, including volatile/non-volatile status register bits (BP2–BP0, TB, SEC, CMP, SRP0/SRP1), individual block/sector lock, and global lock/unlock instructions. Its architecture supports suspend/resume of erase/program operations and configurable output driver strength (DRV1/DRV0).
It operates across -40°C to +85°C with single 2.7–3.6V supply, enabling low-power embedded deployment. The device includes JEDEC-compliant manufacturer/device ID, 64-bit unique serial number, three 256-byte security registers with OTP locks, and SFDP (Serial Flash Discoverable Parameters) register for automatic configuration discovery by host controllers.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 128 M-bit (16 MB), organized as 65,536 × 256-byte pages |
| Interface Modes | Standard SPI, Dual I/O SPI, Quad I/O SPI, and QPI - requires QE bit set for Quad/QPI operation |
| Max Clock Rate | 104 MHz (SPI); enables 208 MHz dual-I/O and 416 MHz quad-I/O effective throughput |
| Erase Granularity | Uniform 4 KB sectors (4,096 total), 32 KB blocks (512), 64 KB blocks (256), and full-chip erase |
| Write Endurance | ≥100,000 program/erase cycles per sector |
| Data Retention | ≥20 years at +25°C; validated under JEDEC JESD22-A117 |
| Power Consumption | 4 mA active (typ.), <1 µA power-down (typ.) - enables battery-backed or ultra-low-power modes |
| Operating Voltage | 2.7 V to 3.6 V - compatible with 3.3 V logic families without level shifting |
Pinout & Package
W25Q128FVSIG uses an 8-pin SOIC 208-mil (Package Code S) with exposed pad not present; pin 1 is /CS, pin 2 is DO (IO1), pin 3 is /WP (IO2), pin 4 is GND, pin 5 is DI (IO0), pin 6 is CLK, pin 7 is /HOLD or /RESET (IO3), and pin 8 is VCC. Pin 7 functions as /HOLD when QE=0 and as /RESET when QE=1 and Status Register-2 HOLD/RST bit = 1.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| /CS (Pin 1) | Chip Select Input | Active-low enable: high = high-Z outputs and standby current; must transition high→low before instruction acceptance post-power-up |
| DO / IO1 (Pin 2) | Data Output / Bidirectional I/O | Unidirectional output in Standard SPI; bidirectional in Dual/Quad SPI; requires QE=1 for Quad mode use |
| /WP / IO2 (Pin 3) | Write Protect Input / Bidirectional I/O | Hardware write-protection for status register when active low; repurposed as IO2 in Quad mode (QE=1) |
| GND (Pin 4) | Ground Reference | Primary return path for VCC and all I/O signals; decoupling capacitor required near pin |
| DI / IO0 (Pin 5) | Data Input / Bidirectional I/O | Unidirectional input in Standard SPI; bidirectional in Dual/Quad SPI; always active as IO0 regardless of QE state |
| CLK (Pin 6) | Serial Clock Input | Rising-edge sampling for input, falling-edge sampling for output; timing-critical for setup/hold compliance |
| /HOLD or /RESET / IO3 (Pin 7) | Hold or Reset Input / Bidirectional I/O | Pauses ongoing SPI transaction when low (/HOLD); resets internal state when pulsed (/RESET); becomes IO3 in Quad mode (QE=1) |
| VCC (Pin 8) | Power Supply | 2.7–3.6 V supply; requires local 0.1 µF ceramic decoupling; tracks /CS during power sequencing |
Key Features
| Feature | Design Value |
|---|---|
| Quad Peripheral Interface (QPI) | Reduces instruction overhead to one 8-bit opcode per transaction, enabling true XIP with minimal CPU intervention |
| Continuous Read Mode with Wrap | Supports 8/16/32/64-byte wrap bursts; achieves sustained 50 MB/s read speed without address retransmission |
| Erase/Program Suspend & Resume | Allows background interrupt servicing during long erase/program cycles - critical for real-time firmware updates |
| Security Registers & Unique ID | Three 256-byte OTP-lockable security registers plus 64-bit factory-programmed unique ID for secure boot and device authentication |
| SFDP Register Compliance | JEDEC JESD216-compliant Serial Flash Discoverable Parameters enable automatic host controller configuration without hard-coded timing tables |
| Flexible Write Protection | Combines hardware (/WP, /HOLD) and software (BPx, TB, SEC, CMP) controls for hierarchical, field-upgradable memory partitioning |
Applications
| IoT Edge Node Firmware Storage | Industrial PLC Boot Memory |
|---|---|
|
Use Scenario: Storing signed firmware images and runtime configuration in battery-powered wireless sensor nodes. IC Role / Device Role / Timing Role: Non-volatile code and data storage with XIP-capable Quad SPI interface for fast boot and OTA update staging. Use Value: 4KB sector granularity enables atomic firmware patching; <1µA power-down current extends battery life over multi-year deployments. |
Use Scenario: Hosting bootloader, RTOS kernel, and HMI assets in programmable logic controllers operating in harsh industrial environments. IC Role / Device Role / Timing Role: Primary boot memory interfaced to ARM Cortex-M7 or RISC-V SoC via QPI for deterministic startup latency. Use Value: 100,000+ erase cycles and 20-year data retention ensure reliability across decades of unattended operation. |
| Automotive ADAS Camera Module | Medical Diagnostic Handheld |
|
Use Scenario: Storing calibration data, image processing firmware, and safety-critical boot code in automotive vision systems. IC Role / Device Role / Timing Role: Secure, AEC-Q100 Grade 3 qualified (via Winbond qualification) storage for ASIL-B functional safety partitions. Use Value: Security registers and unique ID support cryptographic key binding; SFDP enables auto-negotiated timing for varying temperature conditions. |
Use Scenario: Holding FDA-compliant device calibration profiles, user interface assets, and audit logs in portable diagnostic tools. IC Role / Device Role / Timing Role: Trusted non-volatile memory for HIPAA-aligned data integrity, accessed via Dual SPI for EMI-resilient routing on compact PCBs. Use Value: Hardware write protection (/WP pin + BP bits) prevents accidental overwrite of regulatory-critical parameters during field service. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial NOR flash memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MX25L12833FZC-10G | 128M-bit, 104MHz max clock, SOIC-8; lacks QPI mode and SFDP register; uses different status register layout | No native QPI or SFDP - requires fixed timing tables and manual configuration; lower software portability | Choose when QPI/XIP and auto-discovery are unnecessary and legacy SPI-only design reuse is prioritized. |
| S25FL128SAGMFI000 | 128M-bit, 80MHz max clock, SOIC-16; includes dedicated /RESET pin and HyperBus option; supports sector protection but no security registers | Lower bandwidth and no unique ID or OTP security registers - insufficient for secure boot or device identity requirements | Prefer for designs needing guaranteed /RESET independence and HyperBus compatibility, but avoid where cryptographic binding is required. |
Compared with MX25L12833FZC-10G and S25FL128SAGMFI000, W25Q128FVSIG provides higher effective bandwidth via QPI, JEDEC SFDP auto-configuration, and integrated security features - making it optimal for modern embedded systems requiring secure, scalable, and self-describing flash memory.
Availability
W25Q128FVSIG is available at Aetrix Electronics and suitable for IoT edge node firmware storage, industrial PLC boot memory, and automotive ADAS camera module applications requiring stable component supply, long-term lifecycle assurance, and consistent parametric performance.
Supply support for W25Q128FVSIG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Winbond Electronics is a Taiwan-based semiconductor company specializing in specialty DRAM, mobile DRAM, and serial flash memory solutions for consumer, industrial, and automotive markets.
The W25Q series targets high-performance, low-power embedded systems requiring reliable code storage, XIP capability, and advanced security - designed specifically for MCU-based applications demanding robust firmware integrity and field-upgradability.
FAQ
What is the function of Pin 7 (/HOLD or /RESET) on W25Q128FVSIG?
Pin 7 on W25Q128FVSIG serves dual functionality: when the Quad Enable (QE) bit in Status Register-2 is 0, it operates as /HOLD to pause ongoing SPI transactions; when QE=1 and the HOLD/RST bit is set, it functions as /RESET to clear internal state. This behavior is defined in the datasheet Section 3.3 and confirmed by the SOIC-208-mil pin description table.
Does W25Q128FVSIG support execute-in-place (XIP) operation?
Yes, W25Q128FVSIG supports true XIP via Continuous Read Mode and QPI interface. With as few as 8 clocks to address memory and wrap burst support (8/16/32/64-byte), it enables direct code execution from flash without copying to RAM - verified in Section 1 General Descriptions and Section 2 Features of the datasheet.
How does write protection work on W25Q128FVSIG?
W25Q128FVSIG implements layered write protection: hardware-level via /WP pin (active-low, disabled in Quad mode), and software-level via status register bits (BP2–BP0, TB, SEC, CMP, SRP0/SRP1). These allow granular locking of 4KB sectors up to full array, with volatile/non-volatile options - detailed in Sections 6.2 and 7.1 of the datasheet.
What package type does W25Q128FVSIG use?
W25Q128FVSIG uses an 8-pin SOIC 208-mil package (Package Code S), as explicitly stated in Section 11.1 Ordering Information and confirmed by top-side marking "W25Q128FV" and "S" suffix. This matches the pin configuration in Figure 1a and Table 10.1 Package Specifications.
Is W25Q128FVSIG compatible with JEDEC-standard SFDP?
Yes, W25Q128FVSIG fully complies with JEDEC JESD216 for Serial Flash Discoverable Parameters. It implements the SFDP register (readable via instruction 5Ah) to expose timing, density, and feature descriptors - enabling host controllers to auto-configure without hardcoded parameters, as documented in Section 8.2.30 and Section 7.1.14.
W25Q128FVSIG Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Winbond Electronics Corporation
- Series:
- SpiFlash®
- Package/Case:
- 8-SOIC (0.209", 5.30mm Width)
- Packaging:
- Tube
- Product Status:
- Discontinued at Digi-Key
- Programmable:
- Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH - NOR
- Memory Size:
- 128Mbit
- Memory Organization:
- 16M x 8
- Memory Interface:
- SPI - Quad I/O, QPI
- Clock Frequency:
- 104 MHz
- Write Cycle Time - Word, Page:
- 50µs, 3ms
- Access Time:
- -
- Voltage - Supply:
- 2.7V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
W25Q128FVSIG FAQ
1.How can I place an order for W25Q128FVSIG through Aetrix?
Please submit a Request for Quotation (RFQ) for W25Q128FVSIG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for W25Q128FVSIG reliable?
The price and inventory of W25Q128FVSIG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for W25Q128FVSIG is usually 5 days.
3.What payment methods are accepted for W25Q128FVSIG?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for W25Q128FVSIG transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for W25Q128FVSIG?
W25Q128FVSIG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your W25Q128FVSIG order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for W25Q128FVSIG?
For technical support, including W25Q128FVSIG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your W25Q128FVSIG requirements.
6.How does Aetrix verify that W25Q128FVSIG is sourced from the original manufacturer or authorized distributors?
All W25Q128FVSIG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that W25Q128FVSIG meets industry standards.
7.What is the process for return or replacement of W25Q128FVSIG?
All W25Q128FVSIG units undergo pre-shipment inspection (PSI). If there is an issue with W25Q128FVSIG, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The W25Q128FVSIG part is unused and in its original packaging.
Return procedure for W25Q128FVSIG:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
W25Q128FVSIG Tags
-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology
-
AT21CS01-STUM10-T
Microchip Technology
-
AT24C02C-SSHM-T
Microchip Technology
-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics
-
AT24CS02-SSHM-T
Microchip Technology
-
93LC46BT-I/OT
Microchip Technology
-
AT24C04C-SSHM-T
Microchip Technology
-
24LC01BT-I/SN
Microchip Technology
-
24AA02UIDT-I/OT
Microchip Technology
-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
