Winbond Electronics Corporation W25Q128FVSIQ
- Part No.:
- W25Q128FVSIQ
- Manufacturer:
- Winbond Electronics Corporation
- Category:
- Memory
- Package:
- 8-SOIC (0.209", 5.30mm Width)
- Datasheet:
-
W25Q128FVSIQ.pdf
- Description:
- IC FLASH 128MBIT SPI/QUAD 8SOIC
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
W25Q128FVSIQ from Winbond is a 128M-bit (16MB) serial NOR flash memory supporting Standard/Dual/Quad SPI and QPI interfaces, operating at 2.7–3.6V with 104MHz max clock, 4KB uniform sectors, and hardware write protection via /WP and /HOLD pins - used for code storage, XIP execution, and firmware updates in microcontroller-based embedded systems.
For engineers reviewing the W25Q128FVSIQ datasheet, W25Q128FVSIQ pinout, W25Q128FVSIQ application, or W25Q128FVSIQ equivalent, key selection criteria include Quad I/O enable (QE bit), sector-level erase granularity, continuous read mode timing, and package-specific /RESET availability in SOIC-16 vs. 8-pin variants.
Technical Context
The W25Q128FVSIQ implements a flexible SPI-compatible command set with volatile/non-volatile status register control (BP0–BP2, TB, SEC, QE, SRP0/SRP1), enabling configurable memory protection and interface mode selection. Its architecture supports simultaneous instruction/address/data transfer across up to four I/O lines when QE=1, reducing instruction overhead for true execute-in-place (XIP) operation.
It integrates three 256-byte security registers with OTP locks, JEDEC-compliant manufacturer/device ID (9Fh), SFDP register (5Ah), and 64-bit unique serial number (4Bh). Erase/program suspend/resume (75h/7Ah) allows background operations without halting host communication.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 128 M-bit (16 MB), organized as 65,536 × 256-byte pages |
| Interface Modes | Standard SPI (4-wire), Dual SPI (2 I/O), Quad SPI (4 I/O), QPI (4 I/O + dual-cycle instructions) |
| Max Clock Frequency | 104 MHz (SPI), enabling 416 MB/s effective throughput in Quad I/O Fast Read mode |
| Erase Granularity | Uniform 4 KB sectors (4,096 total), plus 32 KB and 64 KB blocks - enables fine-grained firmware partitioning |
| Write Endurance | ≥100,000 program/erase cycles per sector, ensuring long-term reliability in field-updatable systems |
| Data Retention | ≥20 years at +25°C, validated under JEDEC JESD22-A117 stress conditions |
| Operating Voltage | 2.7 V to 3.6 V single supply - compatible with 3.3 V logic domains without level shifting |
| Power Consumption | 4 mA active current (typ.), <1 µA power-down current (typ.) - suitable for battery-backed applications |
Pinout & Package
W25Q128FVSIQ is supplied in an 8-pin SOIC 208-mil (Package Code S) package with exposed pad not present; pin functions are electrically identical to VSOP 208-mil and PDIP 300-mil variants.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| /CS | Chip Select Input | Active-low enable: high = device deselected (high-Z outputs, standby current); low = active communication window |
| DO (IO1) | Data Output / I/O1 | Unidirectional output in Standard SPI; bidirectional I/O in Dual/Quad modes - carries read data or address LSBs |
| /WP (IO2) | Write Protect Input / I/O2 | Hardware lock for status register writes; disabled as I/O2 when Quad Enable (QE=1) is set |
| GND | Ground Reference | Signal and power return path; must be low-impedance to support fast edge rates and noise immunity |
| DI (IO0) | Data Input / I/O0 | Unidirectional input in Standard SPI; bidirectional I/O in Dual/Quad modes - carries commands, addresses, or program data |
| CLK | Serial Clock Input | Master-generated timing signal; rising edge latches input, falling edge samples output - defines maximum interface speed |
| /HOLD or /RESET (IO3) | Hold/Reset Input / I/O3 | Active-low pause signal (when QE=0); becomes I/O3 in Quad mode; dedicated /RESET only on SOIC-16 variant |
| VCC | Power Supply | 2.7–3.6 V core supply; decoupling capacitor required within 10 mm of pin per layout guidelines |
Key Features
| Feature | Design Value |
|---|---|
| Continuous Read Mode | Enables XIP with ≤8-clock instruction overhead per 24-bit address access - eliminates repeated command reissuance |
| Quad Peripheral Interface (QPI) | Dual-cycle instruction encoding reduces command latency and simplifies controller firmware vs. standard SPI opcodes |
| Erase/Program Suspend & Resume | Allows host to interrupt long erase/program operations (e.g., 4KB sector erase ~300 ms) to service higher-priority tasks |
| Individual Sector Lock | 32-byte security registers with OTP locks permit per-sector write-protection independent of BP bits - ideal for bootloader isolation |
| SFDP Register Support | JEDEC JESD216-compliant Serial Flash Discoverable Parameters enables automatic configuration by host boot ROM or FPGA IP |
| Unique 64-bit ID | Factory-programmed serial number accessible via 4Bh instruction - supports secure device authentication and traceability |
Applications
| Industrial PLC Firmware Storage | Automotive Infotainment Boot Memory |
|---|---|
Use Scenario: Storing firmware images and configuration parameters in programmable logic controllers requiring field updates over RS-485 or CAN. IC Role / Device Role / Timing Role: Non-volatile code storage with hardware write protection to prevent accidental corruption during brown-out events. Use Value: 4KB sector erase enables atomic firmware patching without disrupting operational runtime code partitions. | Use Scenario: Hosting boot code and OS kernel for head-unit SoCs where fast sequential read performance is critical for boot time reduction. IC Role / Device Role / Timing Role: Execute-in-place (XIP) memory mapped via Quad SPI interface to eliminate RAM copy latency. Use Value: 416 MB/s effective throughput in Quad I/O Fast Read mode cuts boot time by >35% vs. standard SPI alternatives. |
| Medical Device Configuration Archive | IoT Edge Gateway OTA Storage |
Use Scenario: Retaining calibrated sensor offsets, user preferences, and audit logs in portable diagnostic equipment with strict data integrity requirements. IC Role / Device Role / Timing Role: Parameter storage with individual sector lock and 20-year data retention guarantee. Use Value: Security registers with OTP locks isolate calibration data from application firmware updates, meeting IEC 62304 Class C requirements. | Use Scenario: Holding signed firmware binaries and delta update packages in cellular-connected gateways deployed in remote infrastructure. IC Role / Device Role / Timing Role: Secure, field-upgradable storage with SFDP auto-discovery and unique ID for cloud-based device identity binding. Use Value: 64-bit unique ID and JEDEC ID (9Fh) enable zero-touch provisioning and cryptographic key binding in AWS IoT Core workflows. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial NOR flash memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MX25L12833FZC-10G | 128 M-bit, 104 MHz max clock, but lacks QPI mode and SFDP register; uses different status register layout | No native QPI support limits XIP efficiency in high-performance SoCs; no auto-configurable parameter discovery | Select when legacy SPI-only interface suffices and cost sensitivity outweighs configurability needs |
| S25FL128SAGMFI000 | 128 M-bit, supports Octal DTR mode (up to 400 MHz), includes built-in ECC and sector protection lock bits | Higher bandwidth and error correction suit safety-critical automotive AEC-Q100 Grade 2 applications | Select for ASIL-B systems requiring ECC and extended temperature validation beyond -40°C to +85°C |
Compared with W25Q128FVSIQ, MX25L12833FZC-10G offers lower system integration effort for basic SPI use cases but sacrifices QPI acceleration and SFDP flexibility, while S25FL128SAGMFI000 adds ECC and AEC-Q100 qualification at higher cost and larger footprint - making W25Q128FVSIQ optimal for cost-sensitive industrial and consumer XIP designs.
Availability
W25Q128FVSIQ is available at Aetrix Electronics and suitable for industrial control, medical instrumentation, and IoT edge gateway applications requiring stable component supply, long-lifecycle support, and verified second-source alternatives.
Supply support for W25Q128FVSIQ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Winbond Electronics is a Taiwan-based semiconductor company specializing in specialty memory solutions including NOR/NAND flash, RAM, and mobile DRAM, serving industrial, communications, and consumer markets since 1987.
The W25Q series targets embedded systems needing high-speed, low-power, and secure serial flash - designed specifically for code shadowing, XIP execution, and firmware storage in resource-constrained MCUs and SoCs.
FAQ
What interface protocols does the W25Q128FVSIQ support?
The W25Q128FVSIQ supports Standard SPI (4-wire), Dual SPI (2 I/O), Quad SPI (4 I/O), and Quad Peripheral Interface (QPI) modes. QPI requires setting the Quad Enable (QE) bit in Status Register-2 and uses dual-cycle instruction encoding. All modes operate up to 104 MHz clock frequency, with Quad I/O Fast Read achieving 416 MB/s effective throughput. The W25Q128FVSIQ does not support Octal or DDR modes.
Does W25Q128FVSIQ include hardware write protection features?
Yes, W25Q128FVSIQ provides multiple hardware write protection mechanisms: active-low /WP pin for status register locking, /HOLD pin for operation pausing, and non-volatile status register bits (BP0–BP2, TB, SEC, CMP, SRP0/SRP1) for sector/block-level memory protection. These features allow selective lockdown of boot sectors or configuration regions without software intervention - critical for fail-safe firmware recovery.
What is the erase granularity of W25Q128FVSIQ and how does it impact firmware design?
W25Q128FVSIQ offers uniform 4 KB sector erase (4,096 sectors), plus 32 KB and 64 KB block erase options. This fine granularity enables atomic firmware updates: a new image can be written to spare sectors while the active image runs, then remapped via pointer update. It avoids full-chip erases that cause >1-second downtime - essential for real-time industrial controllers using W25Q128FVSIQ.
Is the /RESET pin available on the W25Q128FVSIQ SOIC-8 package?
No, the W25Q128FVSIQ in SOIC-8 (Package Code S) does not have a dedicated /RESET pin. Pin 7 functions as /HOLD or /RESET depending on the HOLD/RST bit in the status register - but only when Quad Enable (QE) = 0. When QE = 1, that pin becomes IO3 and /RESET is unavailable. For guaranteed hardware reset, use the SOIC-16 variant (Package Code F) which includes a dedicated /RESET pin independent of status register settings.
How does the W25Q128FVSIQ support secure device identity and firmware authenticity?
W25Q128FVSIQ supports secure identity through its factory-programmed 64-bit unique serial number (readable via instruction 4Bh), JEDEC manufacturer/device ID (9Fh), and SFDP register (5Ah) for standardized parameter discovery. Combined with three 256-byte security registers featuring OTP locks, it enables cryptographic key storage and tamper-resistant bootloader verification - foundational for secure boot chains using W25Q128FVSIQ as trusted storage.
W25Q128FVSIQ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Winbond Electronics Corporation
- Series:
- SpiFlash®
- Package/Case:
- 8-SOIC (0.209", 5.30mm Width)
- Packaging:
- Bag
- Product Status:
- Discontinued at Digi-Key
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH - NOR
- Memory Size:
- 128Mbit
- Memory Organization:
- 16M x 8
- Memory Interface:
- SPI - Quad I/O, QPI
- Clock Frequency:
- 104 MHz
- Write Cycle Time - Word, Page:
- 50µs, 3ms
- Access Time:
- -
- Voltage - Supply:
- 2.7V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
W25Q128FVSIQ FAQ
1.How can I place an order for W25Q128FVSIQ through Aetrix?
Please submit a Request for Quotation (RFQ) for W25Q128FVSIQ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for W25Q128FVSIQ reliable?
The price and inventory of W25Q128FVSIQ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for W25Q128FVSIQ is usually 5 days.
3.What payment methods are accepted for W25Q128FVSIQ?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for W25Q128FVSIQ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for W25Q128FVSIQ?
W25Q128FVSIQ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your W25Q128FVSIQ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for W25Q128FVSIQ?
For technical support, including W25Q128FVSIQ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your W25Q128FVSIQ requirements.
6.How does Aetrix verify that W25Q128FVSIQ is sourced from the original manufacturer or authorized distributors?
All W25Q128FVSIQ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that W25Q128FVSIQ meets industry standards.
7.What is the process for return or replacement of W25Q128FVSIQ?
All W25Q128FVSIQ units undergo pre-shipment inspection (PSI). If there is an issue with W25Q128FVSIQ, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The W25Q128FVSIQ part is unused and in its original packaging.
Return procedure for W25Q128FVSIQ:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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