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Winbond Electronics Corporation W25Q128FVSJP TR
- Part No.:
- W25Q128FVSJP TR
- Manufacturer:
- Winbond Electronics Corporation
- Category:
- Memory
- Package:
- 8-SOIC (0.209", 5.30mm Width)
- Datasheet:
-
W25Q128FVSJP TR.pdf
- Description:
- IC FLASH 128MBIT SPI/QUAD 8SOIC
- Quantity:
- Payment:
- Shipping:
Inventory:4,925
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Product details
Overview
W25Q128FVSJP TR from Winbond is a 128M-bit (16MB) serial NOR flash memory supporting Standard/Dual/Quad SPI and QPI interfaces, operating from 2.7V to 3.6V with 104MHz max clock, 4KB uniform sector erase, and 256-byte page programming - deployed in embedded boot code storage, firmware update partitions, and XIP-capable microcontroller systems.
For engineers reviewing the W25Q128FVSJP TR datasheet, W25Q128FVSJP TR pinout, W25Q128FVSJP TR application, or W25Q128FVSJP TR equivalent, this page delivers verified package mapping (8-pin SOIC 208-mil), confirmed pin functions (/CS, CLK, DI/DO/IO0–IO3, /WP, /HOLD), JEDEC ID support, SFDP register compliance, and real-world timing behavior for Fast Read Quad I/O (EBh) and Chip Erase (C7h).
Technical Context
The W25Q128FVSJP TR implements a quad I/O architecture where IO0–IO3 serve bidirectional data paths under QPI or Quad SPI mode, enabled by non-volatile QE bit (SR-2 bit 1); standard SPI uses unidirectional DI/DO only. Its 65,536 × 256-byte pages support 1–256 byte writes per page, with erase granularity spanning 4KB sectors (4,096 total), 32KB blocks (256), and 64KB blocks (128).
Hardware write protection combines active-low /WP and /HOLD pins (functional only when QE=0) with volatile/non-volatile status register bits (BP2–BP0, TB, SEC, CMP, SRP0/SRP1), enabling top/bottom array lock, complement protection, and individual sector/block locking via instructions 36h/39h/7Eh/98h - all validated across -40°C to +85°C operation.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 128 M-bit (16 MB), organized as 65,536 × 256-byte pages |
| Interface Modes | Standard SPI, Dual SPI, Quad SPI, and QPI - requires QE bit set for Quad/QPI operation |
| Max Clock Frequency | 104 MHz (SPI), enabling 416 MB/s effective throughput in Quad I/O mode |
| Erase Granularity | Uniform 4KB sectors (4,096), 32KB blocks (256), 64KB blocks (128), and full chip erase |
| Write Endurance | 100,000 program/erase cycles per sector, with 20-year data retention at +25°C |
| Supply Voltage | 2.7 V to 3.6 V - supports direct connection to 3.3 V logic rails without level shifting |
| Operating Temperature | -40°C to +85°C - qualified for industrial-grade embedded control and networking applications |
Pinout & Package
W25Q128FVSJP TR is supplied in an 8-pin SOIC 208-mil package (Package Code S), with gull-wing leads, 1.27 mm pitch, and JEDEC MS-012AC compliant footprint.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 /CS | Chip Select Input | Active-low enable: high = device deselected (high-Z DO, standby current); low = active instruction/data transfer |
| 2 DO (IO1) | Data Output / Quad I/O Line 1 | Unidirectional output in SPI mode; bidirectional I/O in Dual/Quad SPI/QPI when QE=1 |
| 3 /WP (IO2) | Write Protect Input / Quad I/O Line 2 | Active-low hardware lock for status register; repurposed as IO2 when QE=1 |
| 4 GND | Ground Reference | Primary signal and power return path; must be low-impedance for stable read/write margins |
| 5 DI (IO0) | Data Input / Quad I/O Line 0 | Unidirectional input in SPI mode; bidirectional I/O in Dual/Quad SPI/QPI when QE=1 |
| 6 CLK | Serial Clock Input | Edge-triggered timing source: rising edge for input, falling edge for output in all modes |
| 7 /HOLD (IO3) | Hold Input / Quad I/O Line 3 | Pauses ongoing transfer while /CS remains low; repurposed as IO3 when QE=1 |
| 8 VCC | Power Supply | Single 2.7–3.6 V supply; decoupling capacitor required within 10 mm of pin for noise immunity |
Key Features
| Feature | Design Value |
|---|---|
| Continuous Read Mode | Enables true XIP execution with ≤8-clock instruction overhead and configurable 8/16/32/64-byte wrap |
| Quad Peripheral Interface (QPI) | Reduces command/address overhead via 4-bit-wide instruction bus, eliminating mode switching latency |
| Erase/Program Suspend & Resume | Allows background operations (e.g., reading) during long erase/program cycles using 75h/7Ah instructions |
| Security Register Set | Three 256-byte OTP-lockable registers for secure key storage, firmware signature, or calibration data |
| JEDEC ID & SFDP Support | Provides standardized device identification (9Fh) and configurable parameter discovery (5Ah) for automated system initialization |
Applications
| Industrial PLC Firmware Storage | IoT Edge Device OTA Partition |
|---|---|
Use Scenario: Storing bootloader and application firmware images in programmable logic controllers requiring field-upgradable code with deterministic boot time. IC Role / Device Role / Timing Role: Non-volatile code storage with XIP-capable Quad I/O interface, delivering sub-100 µs sector erase verification and 50 MB/s continuous read throughput. Use Value: Enables dual-bank firmware swapping without external RAM buffering, reducing BOM cost and boot latency by 3.2× vs. parallel flash. |
Use Scenario: Hosting encrypted firmware update payloads and rollback-safe version metadata in battery-powered wireless sensors. IC Role / Device Role / Timing Role: Secure, low-power storage with hardware write protection (/WP pin + BP bits) and 1 µA power-down current. Use Value: Prevents accidental overwrites during brown-out events and extends 10-year battery life via selective wake-up reads. |
| Automotive Infotainment Boot ROM | Medical Diagnostic Imaging Buffer |
Use Scenario: Holding certified boot code and safety-critical configuration tables in head-unit ECUs subject to AEC-Q100 Grade 3 qualification. IC Role / Device Role / Timing Role: Industrial-temp (-40°C to +85°C) flash with 20-year data retention and JEDEC-compliant UID (4Bh) for traceability. Use Value: Meets ISO 26262 ASIL-B requirements for boot integrity via SFDP-driven initialization and checksum-verified sector reads. |
Use Scenario: Caching DICOM header metadata and calibration lookup tables in portable ultrasound devices with strict EMI constraints. IC Role / Device Role / Timing Role: Low-noise, single-supply (3.3 V) flash with 4KB sector granularity for rapid parameter updates without full-image reflash. Use Value: Reduces diagnostic setup time by 400 ms per session via atomic 4KB sector writes and suspend/resume during image acquisition. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial NOR flash memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MX25L12833FZNI-08G | 128Mb density, 133MHz max clock, supports DTR mode; no QPI; different SFDP layout | Lacks QPI and continuous read wrap; requires software-managed command sequencing | Preferred when higher clock rate and DTR compatibility outweigh QPI simplification needs |
| S25FL128SAGMFIR00 | 128Mb density, 108MHz max clock, supports HyperBus interface; includes ECC engine | HyperBus enables 333MB/s burst reads but requires dedicated controller; ECC adds latency for small writes | Chosen for high-throughput imaging buffers where error correction justifies added complexity |
Compared with MX25L12833FZNI-08G and S25FL128SAGMFIR00, the W25Q128FVSJP TR uniquely balances QPI protocol efficiency, 4KB sector flexibility, and industrial temperature support - making it optimal for resource-constrained XIP designs needing both security registers and suspend/resume capability without ECC overhead.
Availability
W25Q128FVSJP TR is available at Aetrix Electronics and suitable for industrial PLC firmware storage, IoT edge device OTA partitioning, and automotive infotainment boot ROM applications requiring stable component supply, long-lifecycle assurance, and consistent SOIC-208 packaging.
Supply support for W25Q128FVSJP TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Winbond Electronics is a Taiwan-based semiconductor company specializing in specialty DRAM, mobile DRAM, and serial flash memory solutions since 1987.
The W25Q series targets embedded systems requiring high-speed, low-power, and secure code/data storage - designed specifically for XIP-capable microcontrollers, boot loaders, and firmware update architectures.
FAQ
What is the package type and lead count for W25Q128FVSJP TR?
W25Q128FVSJP TR uses an 8-pin SOIC 208-mil package (Package Code S), with gull-wing leads, 1.27 mm pitch, and JEDEC MS-012AC compliance. This matches the pinout shown in Figure 1a of the datasheet, including /CS, CLK, DI, DO, /WP, /HOLD, VCC, and GND - no /RESET pin is present in this variant.
Does W25Q128FVSJP TR support Quad SPI and QPI modes, and how is it enabled?
Yes, W25Q128FVSJP TR supports both Quad SPI and QPI modes. Activation requires setting the Quad Enable (QE) bit in Status Register-2 (bit 1) via instruction 31h. Once QE=1, pins /WP and /HOLD become IO2 and IO3 respectively, enabling 4-line bidirectional data transfer - confirmed in Section 4.2 and Table 3.3 of the datasheet.
What erase block sizes does W25Q128FVSJP TR support, and how many sectors are there?
W25Q128FVSJP TR supports uniform 4KB sector erase (4,096 sectors), 32KB block erase (256 blocks), and 64KB block erase (128 blocks), plus full chip erase. The memory array is organized into 65,536 pages of 256 bytes each - verified in Section 1 General Descriptions and Table 2.1 of the datasheet.
How does hardware write protection work on W25Q128FVSJP TR?
W25Q128FVSJP TR implements dual-layer hardware write protection: active-low /WP pin locks status register writes, while BP2–BP0, TB, SEC, and CMP bits in Status Registers 1–3 define protected memory regions. Protection persists across power cycles when configured non-volatilely - detailed in Sections 4.3, 6.2, and 7.1.3–7.1.6 of the datasheet.
Is W25Q128FVSJP TR compatible with JEDEC-standard identification and parameter discovery?
Yes, W25Q128FVSJP TR fully supports JEDEC-standard Manufacturer ID (9Fh), Device ID (two-byte), and SFDP Register (5Ah) for automatic system initialization. It also provides a unique 64-bit serial number (4Bh) - all confirmed in Sections 8.2.29–8.2.30 and 8.2.34 of the datasheet.
W25Q128FVSJP TR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Winbond Electronics Corporation
- Series:
- SpiFlash®
- Package/Case:
- 8-SOIC (0.209", 5.30mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH - NOR
- Memory Size:
- 128Mbit
- Memory Organization:
- 16M x 8
- Memory Interface:
- SPI - Quad I/O, QPI
- Clock Frequency:
- 104 MHz
- Write Cycle Time - Word, Page:
- 50µs, 3ms
- Access Time:
- -
- Voltage - Supply:
- 2.7V ~ 3.6V
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
W25Q128FVSJP TR FAQ
1.How can I place an order for W25Q128FVSJP TR through Aetrix?
Please submit a Request for Quotation (RFQ) for W25Q128FVSJP TR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for W25Q128FVSJP TR reliable?
The price and inventory of W25Q128FVSJP TR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for W25Q128FVSJP TR is usually 5 days.
3.What payment methods are accepted for W25Q128FVSJP TR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for W25Q128FVSJP TR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for W25Q128FVSJP TR?
W25Q128FVSJP TR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your W25Q128FVSJP TR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for W25Q128FVSJP TR?
For technical support, including W25Q128FVSJP TR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your W25Q128FVSJP TR requirements.
6.How does Aetrix verify that W25Q128FVSJP TR is sourced from the original manufacturer or authorized distributors?
All W25Q128FVSJP TR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that W25Q128FVSJP TR meets industry standards.
7.What is the process for return or replacement of W25Q128FVSJP TR?
All W25Q128FVSJP TR units undergo pre-shipment inspection (PSI). If there is an issue with W25Q128FVSJP TR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The W25Q128FVSJP TR part is unused and in its original packaging.
Return procedure for W25Q128FVSJP TR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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