My Inquiry
My Account
Winbond Electronics Corporation W25Q128FWBIQ
- Part No.:
- W25Q128FWBIQ
- Manufacturer:
- Winbond Electronics Corporation
- Category:
- Memory
- Package:
- 24-TBGA
- Datasheet:
-
W25Q128FWBIQ.pdf
- Description:
- IC FLASH 128MBIT SPI 24TFBGA
- Quantity:
- Payment:
- Shipping:
Inventory:1,809
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
W25Q128FWBIQ from Winbond is a 1.65–1.95V, 128M-bit (16MB) serial NOR flash memory supporting Standard/Dual/Quad SPI and QPI interfaces, with 4KB uniform sectors, 104MHz max clock, and hardware write protection via /WP and /HOLD pins - used for code storage, XIP boot, and firmware updates in embedded microcontrollers.
For engineers reviewing the W25Q128FWBIQ datasheet, W25Q128FWBIQ pinout, W25Q128FWBIQ application, or W25Q128FWBIQ equivalent, key selection criteria include voltage compatibility (1.65–1.95V), Quad Enable (QE) bit configuration, sector-erase granularity (4KB), continuous read mode timing, and package-specific /RESET availability (absent in 8-pin SOIC/WSON variants).
Technical Context
The W25Q128FWBIQ implements a dual-mode I/O architecture: Standard SPI uses unidirectional DI/DO with /WP and /HOLD as dedicated control pins; Quad SPI reassigns /WP and /HOLD to IO2 and IO3 when the non-volatile QE bit (Status Register-2, bit 1) is set. It supports true execute-in-place (XIP) via Continuous Read Mode with ≤8-clock instruction overhead and wrap lengths of 8/16/32/64 bytes.
Internal architecture includes a 256-byte page buffer, SFDP register for discoverable parameters, three 256-byte OTP-lockable security registers, and status register bits enabling top/bottom, complement, and individual sector/block protection. Erase suspend/resume and 100,000 program/erase cycles support field-updatable firmware.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 128 M-bit (16 MB), organized as 65,536 × 256-byte pages |
| Supply Voltage | 1.65 V to 1.95 V - enables direct integration with 1.8V logic domains without level shifting |
| Max Clock Frequency | 104 MHz (SPI), enabling 208 MB/s Dual I/O and 416 MB/s Quad I/O effective throughput |
| Erase Granularity | Uniform 4 KB sectors (4,096 total), 32 KB blocks (256), and 64 KB blocks (256) - supports fine-grained firmware partitioning |
| Program/Erase Endurance | 100,000 cycles per sector - validated for frequent OTA update scenarios |
| Data Retention | 20 years at +25°C - meets industrial long-life storage requirements |
| Power Consumption | 4 mA active (typ.), <1 µA power-down (typ.) - suitable for battery-backed or low-power IoT nodes |
Pinout & Package
W25Q128FWBIQ is supplied in an 8-pin SOIC 208-mil (Package Code S) package. Pin functions are fixed per JEDEC-compliant layout and do not vary with operating mode unless Quad Enable (QE) is asserted.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 /CS | Chip Select Input | Active-low enable; high-impedance DO output and standby current when high |
| 2 DO (IO1) | Data Output / Quad I/O 1 | Unidirectional output in Standard SPI; bidirectional I/O in Dual/Quad SPI/QPI |
| 3 /WP (IO2) | Write Protect Input / Quad I/O 2 | Hardware lock for status register when QE=0; becomes IO2 when QE=1 |
| 4 GND | Ground Reference | Signal and power return path; decoupling capacitor must be placed adjacent |
| 5 DI (IO0) | Data Input / Quad I/O 0 | Unidirectional input in Standard SPI; bidirectional I/O in Dual/Quad SPI/QPI |
| 6 CLK | Serial Clock Input | Edge-triggered timing source for all SPI/QPI transfers; requires clean, monotonic edges |
| 7 /HOLD or /RESET (IO3) | Hold or Reset Input / Quad I/O 3 | HOLD function active when QE=0; becomes IO3 in Quad mode; no dedicated /RESET in this package |
| 8 VCC | Power Supply | 1.65–1.95 V supply; requires local 100 nF ceramic decoupling |
Key Features
| Feature | Design Value |
|---|---|
| Quad Peripheral Interface (QPI) | Reduces instruction overhead to single-cycle opcodes, enabling deterministic XIP latency and higher bandwidth than standard SPI |
| Continuous Read Mode | Supports 8/16/32/64-byte wrap with only 8 clocks to address first byte - eliminates address-reload penalty across sequential reads |
| Individual Sector Lock | Enables per-sector (4KB) write protection via Status Register BP bits and security register OTP locks - isolates bootloader from application updates |
| 64-bit Unique ID | Factory-programmed serial number accessible via 4Bh instruction - enables device authentication and secure provisioning |
| JEDEC SFDP Support | Standardized parameter table (5Ah) provides runtime-configurable timing, voltage, and feature discovery - simplifies driver portability |
Applications
| Industrial PLC Firmware Storage | Automotive ADAS Boot Image |
|---|---|
Use Scenario: Storing and verifying boot firmware and configuration data in programmable logic controllers operating in extended temperature (-40°C to +85°C) environments. IC Role / Device Role / Timing Role: Non-volatile code storage with hardware write protection and sector-level locking to prevent accidental corruption during field updates. Use Value: 4KB sector erase enables atomic firmware patching; 20-year data retention ensures reliability over equipment lifetime without refresh. |
Use Scenario: Hosting boot code and sensor calibration tables for vision-based driver-assistance systems requiring AEC-Q100-compliant components. IC Role / Device Role / Timing Role: XIP-capable flash delivering deterministic instruction fetch latency via Continuous Read Mode and QPI interface. Use Value: 104MHz SPI clock with Quad I/O achieves >400 MB/s effective bandwidth - meets real-time boot timing budgets under ASIL-B constraints. |
| IoT Edge Node OTA Updates | Medical Diagnostic Device Configuration |
Use Scenario: Secure over-the-air firmware upgrades in battery-powered wireless sensors with constrained power budgets. IC Role / Device Role / Timing Role: Low-power serial flash with <1 µA power-down current and erase-suspend capability to minimize update window exposure. Use Value: Erase/program suspend (75h/7Ah) allows interruption and resumption of writes - critical for maintaining system responsiveness during updates. |
Use Scenario: Storing calibrated transducer coefficients and regulatory audit logs in portable ultrasound and ECG devices. IC Role / Device Role / Timing Role: Tamper-resistant storage using three 256-byte security registers with OTP lock bits and 64-bit unique ID. Use Value: Security registers provide isolated, write-once storage for cryptographic keys and calibration signatures - satisfies IEC 62304 traceability requirements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial NOR flash applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MX25L12833FZCII00 | 3.3V supply (2.7–3.6V), no QPI mode, 80MHz max clock, 1.5mm SOIC package height | Requires level-shifting for 1.8V systems; lacks QPI acceleration and SFDP register | Select only if legacy 3.3V design exists and QPI/XIP is unnecessary |
| S25FL128SAGMFI000 | 1.7–2.0V supply, 133MHz clock, HyperBus interface option, 10-year data retention | HyperBus enables higher bandwidth but requires different controller IP; shorter retention than W25Q128FWBIQ | Prefer for new designs needing >500 MB/s burst reads, accepting reduced retention guarantee |
Compared with MX25L12833FZCII00 and S25FL128SAGMFI000, W25Q128FWBIQ uniquely balances 1.8V operation, QPI acceleration, 20-year retention, and broad package availability - making it optimal for next-generation low-power, XIP-capable embedded systems where firmware integrity and update flexibility are critical.
Availability
W25Q128FWBIQ is available at Aetrix Electronics and suitable for industrial automation, automotive infotainment, and medical diagnostics requiring stable component supply, long-term lifecycle assurance, and full traceability.
Supply support for W25Q128FWBIQ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Winbond Electronics is a Taiwan-based semiconductor manufacturer specializing in specialty memory solutions, including SPI NOR/NAND flash, RAM, and mobile DRAM.
The W25Q series was designed specifically for embedded code storage and XIP execution in resource-constrained systems - emphasizing low-voltage operation, flexible protection, and interoperable command sets across density grades.
FAQ
What is the supply voltage range for W25Q128FWBIQ?
The W25Q128FWBIQ operates from 1.65 V to 1.95 V. This narrow 1.8V nominal range eliminates the need for external level shifters when interfacing with 1.8V microcontrollers or FPGAs. Operation outside this range may cause unreliable read/write behavior or permanent damage. The device draws only 4 mA during active programming and less than 1 µA in power-down mode, supporting energy-sensitive applications.
Does W25Q128FWBIQ support Quad Peripheral Interface (QPI) mode?
Yes, W25Q128FWBIQ supports QPI mode via the 38h instruction. Enabling QPI requires setting the Quad Enable (QE) bit in Status Register-2. Once enabled, pins /WP and /HOLD become IO2 and IO3, allowing all four I/O lines to carry both address and data. QPI reduces instruction overhead to one clock cycle per opcode and enables faster burst reads than standard SPI - essential for execute-in-place (XIP) performance.
How many 4KB sectors does W25Q128FWBIQ contain?
W25Q128FWBIQ contains exactly 4,096 uniform 4KB sectors. This granularity enables precise firmware partitioning - for example, dedicating separate sectors to bootloader, application image, and configuration data. Each sector can be independently erased, locked, or protected using Block Protect (BP) bits and security registers. Sector erase time is typically 300 ms, and the device guarantees 100,000 erase/program cycles per sector.
Is there a dedicated /RESET pin on the W25Q128FWBIQ package?
No, W25Q128FWBIQ in the 8-pin SOIC 208-mil package (which matches the 'BIQ' suffix) does not include a dedicated /RESET pin. Pin 7 functions as /HOLD when QE=0 or as IO3 when QE=1. Hardware reset capability is only available on the 16-pin SOIC 300-mil variant (package code F). For reset functionality in W25Q128FWBIQ designs, software reset (66h + 99h) or power-cycle sequencing must be used.
Can W25Q128FWBIQ be used for secure firmware storage?
Yes, W25Q128FWBIQ provides multiple hardware-enforced security features for firmware storage: three 256-byte security registers with OTP lock bits, 64-bit factory-unique ID (readable via 4Bh), and configurable sector-level write protection via BP bits and CMP/SEC/TB flags. These features allow isolation of bootloader code, cryptographic keys, and calibration data - meeting baseline requirements for secure boot and regulatory compliance in medical and industrial systems.
W25Q128FWBIQ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Winbond Electronics Corporation
- Series:
- SpiFlash®
- Package/Case:
- 24-TBGA
- Packaging:
- Tray
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH - NOR
- Memory Size:
- 128Mbit
- Memory Organization:
- 16M x 8
- Memory Interface:
- SPI - Quad I/O, QPI
- Clock Frequency:
- 104 MHz
- Write Cycle Time - Word, Page:
- 60µs, 5ms
- Access Time:
- -
- Voltage - Supply:
- 1.65V ~ 1.95V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 24-TFBGA (6x8)
W25Q128FWBIQ FAQ
1.How can I place an order for W25Q128FWBIQ through Aetrix?
Please submit a Request for Quotation (RFQ) for W25Q128FWBIQ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for W25Q128FWBIQ reliable?
The price and inventory of W25Q128FWBIQ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for W25Q128FWBIQ is usually 5 days.
3.What payment methods are accepted for W25Q128FWBIQ?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for W25Q128FWBIQ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for W25Q128FWBIQ?
W25Q128FWBIQ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your W25Q128FWBIQ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for W25Q128FWBIQ?
For technical support, including W25Q128FWBIQ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your W25Q128FWBIQ requirements.
6.How does Aetrix verify that W25Q128FWBIQ is sourced from the original manufacturer or authorized distributors?
All W25Q128FWBIQ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that W25Q128FWBIQ meets industry standards.
7.What is the process for return or replacement of W25Q128FWBIQ?
All W25Q128FWBIQ units undergo pre-shipment inspection (PSI). If there is an issue with W25Q128FWBIQ, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The W25Q128FWBIQ part is unused and in its original packaging.
Return procedure for W25Q128FWBIQ:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
W25Q128FWBIQ Tags
-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology
-
AT21CS01-STUM10-T
Microchip Technology
-
AT24C02C-SSHM-T
Microchip Technology
-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics
-
AT24CS02-SSHM-T
Microchip Technology
-
93LC46BT-I/OT
Microchip Technology
-
AT24C04C-SSHM-T
Microchip Technology
-
24LC01BT-I/SN
Microchip Technology
-
24AA02UIDT-I/OT
Microchip Technology
-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
