Winbond Electronics Corporation W25Q128FWEIG TR
- Part No.:
- W25Q128FWEIG TR
- Manufacturer:
- Winbond Electronics Corporation
- Category:
- Memory
- Package:
- 8-WDFN Exposed Pad
- Datasheet:
-
W25Q128FWEIG TR.pdf
- Description:
- IC FLASH 128MBIT SPI/QUAD 8WSON
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
W25Q128FWEIG TR from Winbond is a 1.8V, 128M-bit serial NOR flash memory with Dual/Quad SPI and QPI interfaces, organized as 65,536 × 256-byte pages, supporting 4KB sector/32KB–64KB block erase, and offering 104MHz SPI clock (416MHz Quad I/O equivalent) for XIP-capable code storage in microcontroller boot applications.
For engineers reviewing the W25Q128FWEIG TR datasheet, W25Q128FWEIG TR pinout, W25Q128FWEIG TR application, or W25Q128FWEIG TR equivalent, key selection criteria include its 1.65–1.95V supply range, <1µA power-down current, JEDEC ID and SFDP register support, 64-bit unique ID, and hardware write protection via /WP and /HOLD pins in standard SPI mode.
Technical Context
The W25Q128FWEIG TR implements a unified SPI/QPI command architecture with configurable IO0–IO3 pins: in Standard/Dual SPI, /WP and /HOLD retain dedicated functions; in Quad SPI mode (QE=1), those pins become IO2 and IO3. Its status register includes volatile/non-volatile BP2–BP0, TB, SEC, CMP, SRP0/SRP1, QE, and DRV0/DRV1 bits for granular memory protection and driver strength control.
It supports true execute-in-place (XIP) via Continuous Read Mode with ≤8-clock instruction overhead and wrap lengths of 8/16/32/64 bytes. Erase/program suspend/resume enables concurrent background operations, while three 256-byte OTP-locked security registers provide secure parameter storage independent of main array access.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 128 M-bit (16 MB), organized as 65,536 × 256-byte programmable pages |
| Supply Voltage | 1.65 V to 1.95 V - enables direct integration with 1.8V logic domains without level shifting |
| SPI Clock Max | 104 MHz - delivers up to 50 MB/s continuous read throughput in Quad I/O mode |
| Erase Granularity | 4 KB sectors (4,096 total), 32 KB blocks (2,048), 64 KB blocks (256) - supports fine-grained firmware update partitioning |
| Endurance & Retention | 100,000 program/erase cycles; 20-year data retention at +85°C - suitable for field-upgradable embedded systems |
| Interface Modes | Standard SPI (4-wire), Dual SPI (4-wire), Quad SPI (4-wire), QPI (6-wire) - selectable via QE bit and instruction set |
| Security Features | 64-bit unique ID, JEDEC ID, SFDP register, three 256-byte OTP-lockable security registers - enables device authentication and secure boot key storage |
Pinout & Package
W25Q128FWEIG TR uses an 8-pin WSON 6×5-mm package (Package Code P), with exposed pad for thermal dissipation and space-constrained PCB layouts.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| /CS | Chip Select Input | Active-low enable; high-impedance DO during deselect; required high-to-low transition before instruction acceptance |
| DO (IO1) | Data Output / Bidirectional I/O | Unidirectional output in Standard SPI; bidirectional in Dual/Quad SPI; shares pin with IO1 per JEDEC SPI conventions |
| /WP (IO2) | Write Protect Input / Bidirectional I/O | Hardware lock for status register when QE=0; becomes IO2 in Quad SPI mode (QE=1) |
| GND | Ground Reference | Primary return path for all internal circuitry and I/O drivers; must be low-impedance for noise immunity |
| DI (IO0) | Data Input / Bidirectional I/O | Unidirectional input in Standard SPI; bidirectional in Dual/Quad SPI; shares pin with IO0 per JEDEC SPI conventions |
| CLK | Serial Clock Input | Master-generated timing reference for all SPI/QPI transfers; rising edge samples inputs, falling edge drives outputs |
| /HOLD or /RESET (IO3) | Hold/Reset Input / Bidirectional I/O | Pauses ongoing SPI transfer when active low (QE=0); becomes IO3 in Quad SPI; dedicated /RESET only on 16-pin SOIC variant |
| VCC | Power Supply | 1.65–1.95 V core supply; powers memory array, control logic, and I/O buffers; requires local decoupling |
Key Features
| Feature | Design Value |
|---|---|
| Continuous Read Mode | Enables true XIP with ≤8-clock instruction overhead and configurable 8/16/32/64-byte wrap - eliminates address retransmission latency |
| Quad Peripheral Interface (QPI) | Reduces instruction overhead via 2-clock-cycle opcodes - allows full-duplex 4-bit-wide transfers without mode switching |
| Erase/Program Suspend & Resume | Permits background erase or program to pause for higher-priority reads - critical for real-time firmware update scenarios |
| Volatile/Non-Volatile Status Register Bits | BP2–BP0, TB, SEC, CMP, SRP0/SRP1, QE, DRV0/DRV1 allow persistent or runtime-configurable memory protection and drive strength |
| Three 256-byte Security Registers | OTP-lockable storage for cryptographic keys or calibration data - isolated from main array and inaccessible via standard read commands |
Applications
| Microcontroller Boot Memory | Firmware Over-the-Air (OTA) Storage |
|---|---|
Use Scenario: Storing boot code for ARM Cortex-M or RISC-V MCUs that execute directly from flash via XIP. IC Role / Device Role / Timing Role: Primary non-volatile code storage with deterministic 104MHz SPI access and 4KB sector granularity for bootloader updates. Use Value: Eliminates external RAM copy step; reduces BOM cost and boot time by enabling direct execution from W25Q128FWEIG TR's 4KB erasable sectors. | Use Scenario: Holding staged firmware images in IoT edge devices prior to validated activation. IC Role / Device Role / Timing Role: Dual-bank storage partitioned into protected sectors - one active, one staging - managed via BP bits and erase suspend. Use Value: Enables atomic firmware swaps with zero downtime using W25Q128FWEIG TR's sector-level protection and suspend/resume capability. |
| Industrial HMI Display Cache | Secure Key Storage for Trusted Execution |
Use Scenario: Caching GUI assets (fonts, icons, bitmaps) in PLC touch panels with limited DRAM. IC Role / Device Role / Timing Role: High-throughput Quad SPI data source delivering >40 MB/s bursts to display controller DMA engines. Use Value: Leverages W25Q128FWEIG TR's 50 MB/s continuous read rate and wrap-mode efficiency to sustain 60 Hz UI refresh without frame drops. | Use Scenario: Storing AES-256 keys and device certificates in medical or automotive ECUs requiring tamper resistance. IC Role / Device Role / Timing Role: Isolated OTP-locked security register bank accessed only via dedicated 42h/48h/44h instructions. Use Value: Prevents key extraction via bus snooping or firmware dump by physically separating keys from main array and enforcing OTP lock after programming. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial NOR flash memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MX25L12833FZC-10G | 3V supply (2.7–3.6V), no QPI mode, 80MHz max SPI clock, lacks SFDP and unique ID | Requires level-shifting for 1.8V systems; no XIP optimization; limited configuration discovery | Select only if legacy 3V design compatibility is mandatory and Quad I/O/XIP are unused. |
| S25FL128SAGMFI000 | 1.8V supply, 133MHz SPI, HyperBus interface option, integrated ECC, no /HOLD pin in 8-pin WSON | Higher bandwidth but larger footprint; HyperBus adds controller complexity; missing /HOLD limits SPI bus sharing | Prefer for bandwidth-critical applications with HyperBus-capable SoCs; avoid when /HOLD-driven multi-device arbitration is required. |
Compared with MX25L12833FZC-10G, W25Q128FWEIG TR delivers 1.8V-native operation and QPI for lower instruction overhead, while versus S25FL128SAGMFI000 it retains /HOLD functionality in compact WSON and avoids HyperBus licensing complexity - making it optimal for cost-sensitive, space-constrained XIP designs.
Availability
W25Q128FWEIG TR is available at Aetrix Electronics and suitable for microcontroller boot memory, OTA firmware storage, industrial HMI caching, and secure key storage requiring stable component supply across automotive, industrial, and consumer electronics programs.
Supply support for W25Q128FWEIG TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Winbond Electronics is a Taiwan-based semiconductor manufacturer specializing in specialty memory solutions, including SPI NOR/NAND flash, RAM, and mobile DRAM.
The W25Q series targets embedded systems needing high-speed, low-voltage, secure serial flash for code execution and firmware storage - emphasizing XIP capability, flexible protection, and compact packaging.
FAQ
What is the operating voltage range of the W25Q128FWEIG TR?
The W25Q128FWEIG TR operates from 1.65 V to 1.95 V, making it compatible with 1.8V logic families without level shifters. This narrow range ensures stable performance in battery-powered and low-power embedded systems, and its typical power-down current is under 1 µA - critical for always-on IoT nodes. The W25Q128FWEIG TR's voltage tolerance is verified across the full -40°C to +85°C industrial temperature range.
Does the W25Q128FWEIG TR support execute-in-place (XIP) operation?
Yes, the W25Q128FWEIG TR supports true XIP via Continuous Read Mode, which requires only 8 clocks to initiate a read sequence and supports 8/16/32/64-byte wrap lengths. This minimizes instruction overhead and enables deterministic code fetch timing - essential for real-time MCU boot and application execution. The W25Q128FWEIG TR achieves up to 50 MB/s sustained read throughput in Quad I/O mode, outperforming parallel flash in bandwidth-per-pin efficiency.
How does the /WP and /HOLD pin behavior change in Quad SPI mode?
In Quad SPI mode (enabled by setting the QE bit in Status Register-2), the /WP and /HOLD pins of the W25Q128FWEIG TR are reassigned as IO2 and IO3, respectively - disabling their hardware protection and hold functions. This trade-off enables full 4-bit bidirectional data transfer but requires software-based write protection (e.g., BP bits) and alternative bus arbitration strategies. The W25Q128FWEIG TR's datasheet explicitly states this functional shift in Sections 4.3 and 4.4.
What security features does the W25Q128FWEIG TR provide beyond basic write protection?
Beyond BP bits and /WP pin control, the W25Q128FWEIG TR includes a 64-bit unique serial number, JEDEC-standard manufacturer/device ID, SFDP register for auto-configuration, and three 256-byte security registers with OTP locking. These registers are accessible only via dedicated instructions (42h/48h/44h) and are isolated from main array reads - preventing exposure during firmware dumps. The W25Q128FWEIG TR's security model supports secure boot key storage and device identity binding in certified applications.
Is the W25Q128FWEIG TR pin-compatible with earlier W25Q128FV or W25Q128JV variants?
No - the W25Q128FWEIG TR is not pin-compatible with W25Q128FV or W25Q128JV due to differences in pin function mapping and package options. While all share the same 8-pin WSON 6×5-mm footprint, the W25Q128FVEIG TR integrates /HOLD and /RESET on the same pin (IO3) with mode-selectable behavior, whereas FV/JV variants use fixed /HOLD only. The W25Q128FWEIG TR's datasheet confirms this distinction in Section 3.3 and Figure 1b, requiring layout review before substitution.
W25Q128FWEIG TR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Winbond Electronics Corporation
- Series:
- SpiFlash®
- Package/Case:
- 8-WDFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH - NOR
- Memory Size:
- 128Mbit
- Memory Organization:
- 16M x 8
- Memory Interface:
- SPI - Quad I/O, QPI
- Clock Frequency:
- 104 MHz
- Write Cycle Time - Word, Page:
- 60µs, 5ms
- Access Time:
- -
- Voltage - Supply:
- 1.65V ~ 1.95V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-WSON (8x6)
W25Q128FWEIG TR FAQ
1.How can I place an order for W25Q128FWEIG TR through Aetrix?
Please submit a Request for Quotation (RFQ) for W25Q128FWEIG TR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for W25Q128FWEIG TR reliable?
The price and inventory of W25Q128FWEIG TR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for W25Q128FWEIG TR is usually 5 days.
3.What payment methods are accepted for W25Q128FWEIG TR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for W25Q128FWEIG TR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for W25Q128FWEIG TR?
W25Q128FWEIG TR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your W25Q128FWEIG TR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for W25Q128FWEIG TR?
For technical support, including W25Q128FWEIG TR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your W25Q128FWEIG TR requirements.
6.How does Aetrix verify that W25Q128FWEIG TR is sourced from the original manufacturer or authorized distributors?
All W25Q128FWEIG TR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that W25Q128FWEIG TR meets industry standards.
7.What is the process for return or replacement of W25Q128FWEIG TR?
All W25Q128FWEIG TR units undergo pre-shipment inspection (PSI). If there is an issue with W25Q128FWEIG TR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The W25Q128FWEIG TR part is unused and in its original packaging.
Return procedure for W25Q128FWEIG TR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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