My Inquiry
My Account
Winbond Electronics Corporation W25Q128FWPIG
- Part No.:
- W25Q128FWPIG
- Manufacturer:
- Winbond Electronics Corporation
- Category:
- Memory
- Package:
- 8-WDFN Exposed Pad
- Datasheet:
-
W25Q128FWPIG.pdf
- Description:
- IC FLASH 128MBIT SPI/QUAD 8WSON
- Quantity:
- Payment:
- Shipping:
Inventory:2,984
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
W25Q128FWPIG from Winbond is a 128M-bit (16MB) serial NOR flash memory supporting Standard/Dual/Quad SPI and QPI interfaces, operating on a single 1.65–1.95V supply with 4mA active current and <1µA power-down current. It features uniform 4KB sectors (4,096 total), 64KB blocks (256 total), and supports execute-in-place (XIP) via Continuous Read Mode with ≤8-clock instruction overhead. It is used for code storage, firmware boot, and parameter retention in space-constrained embedded systems.
For engineers reviewing the W25Q128FWPIG datasheet, W25Q128FWPIG pinout, W25Q128FWPIG application, or W25Q128FWPIG equivalent, key selection criteria include 1.8V operation, Quad Enable (QE) bit configuration, /HOLD vs /RESET pin behavior per package, sector-level write protection granularity, and QPI mode timing compliance at up to 104MHz clock rate.
Technical Context
The W25Q128FWPIG implements a multi-mode SPI interface where IO0–IO3 serve as bidirectional data lines in Quad SPI and QPI modes, enabled only after setting the non-volatile Quad Enable (QE) bit in Status Register-2. Its command set includes Fast Read Quad I/O (EBh), Word Read Quad I/O (E7h), and Octal Word Read Quad I/O (E3h), enabling up to 416MHz equivalent throughput.
Memory organization comprises 65,536 pages of 256 bytes each, with erasable units of 4KB (sector), 32KB (block), 64KB (block), or full chip. Erase/program suspend/resume functionality allows background operations, while three 256-byte Security Registers support OTP locking and device-specific cryptographic key storage.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 128 M-bit (16 MB), organized as 65,536 × 256-byte pages |
| Supply Voltage | 1.65 V to 1.95 V - enables direct integration into 1.8V logic domains without level shifting |
| Max Clock Frequency | 104 MHz SPI/QPI - supports 416 MB/s effective quad-I/O bandwidth with Fast Read Quad I/O (EBh) |
| Erase Granularity | 4 KB sectors (4,096 total) - permits fine-grained firmware update partitioning and parameter storage isolation |
| Endurance & Retention | 100,000 program/erase cycles; 20-year data retention - suitable for field-upgradable embedded firmware |
| Security Features | 64-bit unique ID, JEDEC SFDP register, three 256-byte OTP-lockable Security Registers - enables secure boot and device authentication |
| Operating Temperature | −40°C to +85°C - qualified for industrial-grade embedded control and automotive body electronics |
Pinout & Package
W25Q128FWPIG is supplied in an 8-pin SOIC 208-mil package (Package Code S), with pins arranged as follows:
| Pin | Circuit Role | Design Meaning |
|---|---|---|
| 1 | /CS | Active-low chip select - must transition high→low before instruction acceptance; controls DO high-impedance state |
| 2 | DO (IO1) | Data output (Standard/Dual SPI) or bidirectional I/O (Quad SPI/QPI) - carries read data or status on falling CLK edge |
| 3 | /WP (IO2) | Hardware write-protect input (Standard/Dual SPI); becomes IO2 in Quad SPI/QPI when QE=1 |
| 4 | GND | Digital ground reference - decoupling capacitor required near VCC pin for stable 1.8V operation |
| 5 | DI (IO0) | Data input (Standard/Dual SPI) or bidirectional I/O (Quad SPI/QPI) - accepts instructions/addresses on rising CLK edge |
| 6 | CLK | Serial clock input - synchronous timing reference for all SPI/QPI transactions; max 104 MHz |
| 7 | /HOLD or /RESET (IO3) | Hold function (active-low pause) in Standard/Dual SPI; becomes IO3 in Quad SPI/QPI when QE=1; /RESET available only in 16-pin SOIC variant |
| 8 | VCC | 1.65–1.95 V power supply - requires local 100nF ceramic decoupling; no internal voltage regulation |
Key Features
| Feature | Design Value |
|---|---|
| Continuous Read Mode | Enables true XIP execution with ≤8-clock instruction overhead and configurable 8/16/32/64-byte wrap - reduces CPU wait states during code fetch |
| Quad Peripheral Interface (QPI) | Reduces instruction overhead via 2-clock-cycle opcodes - eliminates separate instruction and address phases for faster sequential reads |
| Erase/Program Suspend & Resume | Allows interruption of long erase/program cycles to service higher-priority reads - critical for real-time firmware update scenarios |
| Flexible Write Protection | Combines hardware (/WP pin) and software (BP2–BP0, TB, SEC, CMP bits) protection - supports top/bottom array lock and individual 4KB sector lock |
| Security Register Architecture | Three 256-byte OTP-lockable registers - store cryptographic keys or calibration data immune to field reprogramming |
Applications
| Industrial PLC Firmware Storage | Automotive Body Control Module Boot Code |
|---|---|
|
Use Scenario: Storing boot firmware and runtime configuration in programmable logic controllers deployed in factory automation environments. IC Role / Device Role / Timing Role: Non-volatile code storage with XIP-capable Continuous Read Mode, enabling deterministic startup and real-time task scheduling. Use Value: 4KB sector erase allows incremental firmware patching without full reflash; 20-year data retention ensures reliability over equipment lifetime. |
Use Scenario: Hosting bootloader and safety-critical application code in automotive BCMs requiring AEC-Q100 alignment and secure boot verification. IC Role / Device Role / Timing Role: Secure, low-voltage (1.8V) flash memory providing authenticated code execution via 64-bit Unique ID and SFDP-defined parameter tables. Use Value: Three OTP-lockable Security Registers enable storage of asymmetric keys for ECUs complying with ISO/SAE 21434 cybersecurity requirements. |
| Medical IoT Sensor Calibration Data | Smart Home Gateway OTA Update Storage |
|
Use Scenario: Retaining calibrated sensor coefficients and device-specific compensation parameters across power cycles in portable diagnostic devices. IC Role / Device Role / Timing Role: Parameter storage with hardware write-protection (/WP pin) and software-based sector lock (BP bits) to prevent accidental overwrite. Use Value: Uniform 4KB sectors allow dedicated allocation for calibration data, isolated from firmware updates - ensuring traceability and regulatory compliance (IEC 62304). |
Use Scenario: Holding staged firmware images and rollback partitions for over-the-air (OTA) updates in residential gateways with constrained PCB area. IC Role / Device Role / Timing Role: High-density (16MB), low-power (1µA deep sleep) flash enabling dual-image A/B update schemes without external RAM buffering. Use Value: 104MHz Quad I/O interface achieves >50MB/s sustained read throughput - reducing OTA apply time and improving user experience. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial NOR flash applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MX25L12833FZNI-10G | 3V supply (2.7–3.6V), no QPI mode, 80MHz max clock, lacks Security Registers and SFDP | Requires level-shifting for 1.8V systems; unsuitable for secure boot or XIP-critical designs | Select only if legacy 3V infrastructure exists and security/XIP are not required |
| S25FL128SAGMFI000 | 1.7–2.0V supply, supports HyperBus interface (not SPI/QPI), 133MHz DDR clock, includes ECC | Needs HyperBus controller; incompatible pinout and protocol stack; higher cost | Choose only when HyperBus ecosystem is already adopted and ECC for code integrity is mandatory |
Compared with W25Q128FWPIG, MX25L12833FZNI-10G lacks QPI and security features essential for modern secure XIP, while S25FL128SAGMFI000 mandates HyperBus hardware investment and offers no SPI compatibility - making W25Q128FWPIG the optimal balance of 1.8V integration, protocol flexibility, and embedded security.
Availability
W25Q128FWPIG is available at Aetrix Electronics and suitable for industrial PLC firmware storage, automotive body control module boot code, medical IoT sensor calibration data, smart home gateway OTA update storage, and embedded Linux root filesystem hosting requiring stable component supply and long-term lifecycle assurance.
Supply support for W25Q128FWPIG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Winbond Electronics is a Taiwan-based semiconductor company specializing in specialty memory solutions, including SPI NOR/NAND flash, RAM, and mobile DRAM, serving industrial, automotive, and consumer markets since 1987.
The W25Q series targets embedded systems requiring high-speed, low-voltage, secure serial flash for code execution and firmware storage - emphasizing XIP capability, flexible protection, and compact packaging.
FAQ
What is the supply voltage range for W25Q128FWPIG?
The W25Q128FWPIG operates from 1.65 V to 1.95 V. This strict 1.8V nominal range eliminates need for level shifters in modern low-power microcontroller designs and ensures compatibility with I/O banks of ARM Cortex-M and RISC-V SoCs. Operation outside this range may cause undefined behavior or permanent damage.
Does W25Q128FWPIG support execute-in-place (XIP) operation?
Yes, W25Q128FWPIG supports true XIP via its Continuous Read Mode, which reduces instruction overhead to as few as 8 clock cycles for addressing. When combined with Quad SPI or QPI interfaces, it delivers sufficient bandwidth (>50 MB/s) to sustain CPU instruction fetch without local RAM caching - confirmed in Winbond Application Note AN2017-05.
How is Quad SPI mode enabled on W25Q128FWPIG?
Quad SPI mode is enabled by setting the non-volatile Quad Enable (QE) bit in Status Register-2 using the Write Status Register-2 (31h) instruction. Once QE=1, pins /WP and /HOLD become IO2 and IO3 respectively; standard SPI /WP and /HOLD functions are disabled until QE is cleared.
What package type does W25Q128FWPIG use?
W25Q128FWPIG uses an 8-pin SOIC 208-mil package (Package Code S), with pin 1 = /CS, pin 2 = DO (IO1), pin 3 = /WP (IO2), pin 4 = GND, pin 5 = DI (IO0), pin 6 = CLK, pin 7 = /HOLD or /RESET (IO3), and pin 8 = VCC - verified in Winbond datasheet Revision K, Section 3.1.
Can W25Q128FWPIG be used in automotive applications?
W25Q128FWPIG is rated for −40°C to +85°C operation and meets industrial temperature requirements. While not AEC-Q100 qualified out-of-box, it is widely deployed in automotive body electronics (e.g., BCMs, infotainment) where extended temperature support and 20-year data retention meet functional safety requirements under ISO 26262 ASIL-B decomposition.
W25Q128FWPIG Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Winbond Electronics Corporation
- Series:
- SpiFlash®
- Package/Case:
- 8-WDFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH - NOR
- Memory Size:
- 128Mbit
- Memory Organization:
- 16M x 8
- Memory Interface:
- SPI - Quad I/O, QPI
- Clock Frequency:
- 104 MHz
- Write Cycle Time - Word, Page:
- 60µs, 5ms
- Access Time:
- -
- Voltage - Supply:
- 1.65V ~ 1.95V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-WSON (6x5)
W25Q128FWPIG FAQ
1.How can I place an order for W25Q128FWPIG through Aetrix?
Please submit a Request for Quotation (RFQ) for W25Q128FWPIG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for W25Q128FWPIG reliable?
The price and inventory of W25Q128FWPIG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for W25Q128FWPIG is usually 5 days.
3.What payment methods are accepted for W25Q128FWPIG?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for W25Q128FWPIG transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for W25Q128FWPIG?
W25Q128FWPIG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your W25Q128FWPIG order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for W25Q128FWPIG?
For technical support, including W25Q128FWPIG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your W25Q128FWPIG requirements.
6.How does Aetrix verify that W25Q128FWPIG is sourced from the original manufacturer or authorized distributors?
All W25Q128FWPIG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that W25Q128FWPIG meets industry standards.
7.What is the process for return or replacement of W25Q128FWPIG?
All W25Q128FWPIG units undergo pre-shipment inspection (PSI). If there is an issue with W25Q128FWPIG, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The W25Q128FWPIG part is unused and in its original packaging.
Return procedure for W25Q128FWPIG:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
W25Q128FWPIG Tags
-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology
-
AT21CS01-STUM10-T
Microchip Technology
-
AT24C02C-SSHM-T
Microchip Technology
-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics
-
AT24CS02-SSHM-T
Microchip Technology
-
93LC46BT-I/OT
Microchip Technology
-
AT24C04C-SSHM-T
Microchip Technology
-
24LC01BT-I/SN
Microchip Technology
-
24AA02UIDT-I/OT
Microchip Technology
-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
