Winbond Electronics Corporation W25Q128FWPIG TR
- Part No.:
- W25Q128FWPIG TR
- Manufacturer:
- Winbond Electronics Corporation
- Category:
- Memory
- Package:
- 8-WDFN Exposed Pad
- Datasheet:
-
W25Q128FWPIG TR.pdf
- Description:
- IC FLASH 128MBIT SPI/QUAD 8WSON
- Quantity:
- Payment:

- Shipping:

Inventory:4,425
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
W25Q128FWPIG TR from Winbond is a 1.8V, 128M-bit (16MB) serial NOR flash memory supporting Standard/Dual/Quad SPI and QPI interfaces, organized into 65,536 × 256-byte pages with 4KB uniform sector erase, 32KB/64KB block erase, and chip erase - used for code storage, XIP execution, and firmware parameter retention in space-constrained embedded systems.
For engineers reviewing the W25Q128FWPIG TR datasheet, W25Q128FWPIG TR pinout, W25Q128FWPIG TR application, or W25Q128FWPIG TR equivalent, key selection criteria include 104MHz SPI clock support, Quad Enable (QE) bit configuration, /HOLD or /RESET dual-function pin behavior, and 1.65–1.95V supply compatibility with <1µA power-down current.
Technical Context
The W25Q128FWPIG TR implements a multi-mode serial interface: Standard SPI uses DI/DO unidirectionally; Dual/Quad SPI repurpose /WP and /HOLD as IO2/IO3 when QE=1; QPI enables 2-clock instruction cycles for reduced overhead. Its status register includes volatile/non-volatile BP2–BP0, TB, SEC, CMP, SRP0/SRP1, and QE bits controlling protection and I/O mode.
Memory architecture supports erase/program suspend/resume, continuous read with wrap (8/16/32/64-byte), and true execute-in-place (XIP) via Fast Read Quad I/O (EBh) delivering up to 416MHz effective throughput. Security features include three 256-byte OTP-lockable security registers, 64-bit unique ID, and SFDP register for discoverable parameters.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 128 M-bit (16 MB) - supports full firmware images and boot code in compact footprint |
| Supply Voltage | 1.65 V to 1.95 V - compatible with low-voltage SoC I/O domains and battery-powered designs |
| SPI Clock Max | 104 MHz - enables 50 MB/s continuous read via Fast Read Quad I/O (EBh) |
| Erase Granularity | 4 KB sectors (4,096 total), 32 KB/64 KB blocks - allows fine-grained firmware update partitioning |
| Endurance & Retention | 100,000 program/erase cycles, 20-year data retention - suitable for field-upgradable industrial firmware |
| Interface Modes | Standard/Dual/Quad SPI + QPI - selectable via QE bit; /WP and /HOLD become IO2/IO3 in Quad mode |
| Power Consumption | 4 mA active (typ), <1 µA power-down (typ) - critical for always-on IoT sensor nodes |
Pinout & Package
W25Q128FWPIG TR is packaged in an 8-pin SOIC 208-mil (Package Code S) with exposed pad not present; pin functions are identical to W25Q128FW SOIC-8 per datasheet Figure 1a and Section 3.3.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 /CS | Chip Select Input | Active-low enable; high-impedance DO and standby current when deasserted |
| 2 DO (IO1) | Data Output / I/O1 | Unidirectional output in Standard SPI; bidirectional I/O in Dual/Quad modes |
| 3 /WP (IO2) | Write Protect Input / I/O2 | Hardware lock for status register when QE=0; becomes IO2 in Quad mode (QE=1) |
| 4 GND | Ground Reference | Signal and power return path; decoupling capacitor required near VCC pin |
| 5 DI (IO0) | Data Input / I/O0 | Unidirectional input in Standard SPI; bidirectional I/O in Dual/Quad modes |
| 6 CLK | Serial Clock Input | Edge-triggered timing source; rising edge for input, falling edge for output |
| 7 /HOLD or /RESET (IO3) | Hold/Reset Input / I/O3 | Pauses ongoing operation when low; configurable as /RESET only if QE=0 and SOIC-8 package |
| 8 VCC | Power Supply | 1.65–1.95 V supply; requires local 100 nF ceramic decoupling |
Key Features
| Feature | Design Value |
|---|---|
| Quad Peripheral Interface (QPI) | Reduces instruction overhead to 2 clocks per command, enabling deterministic XIP latency |
| Erase/Program Suspend & Resume | Allows background firmware update without interrupting real-time application execution |
| Three 256-byte Security Registers | OTP-lockable storage for cryptographic keys or calibration data inaccessible via standard read commands |
| 64-bit Unique Serial Number | Enables device-level traceability and secure provisioning in production programming |
| JEDEC SFDP Register | Self-describing flash parameters (timing, density, erase sizes) for automatic driver initialization |
Applications
| Industrial PLC Firmware Storage | Automotive ADAS Boot Memory |
|---|---|
Use Scenario: Storing bootloader and safety-critical firmware in programmable logic controllers requiring field updates over CAN or Ethernet. IC Role / Device Role / Timing Role: Non-volatile code storage with XIP capability and hardware write protection for immutable boot code. Use Value: 4KB sector erase enables delta updates without full reflash; 20-year retention ensures lifetime firmware integrity in unattended deployments. | Use Scenario: Holding boot code and sensor fusion algorithms in automotive camera modules operating across -40°C to +85°C. IC Role / Device Role / Timing Role: Primary boot memory interfaced to ARM Cortex-R5 MCU via Quad SPI at 80MHz for sub-100ms cold boot. Use Value: 104MHz clock support and Fast Read Quad I/O deliver >40MB/s effective bandwidth, meeting ASIL-B timing constraints. |
| IoT Edge Node Configuration | Medical Device Parameter Storage |
Use Scenario: Storing calibrated sensor offsets, network credentials, and OTA update staging area in battery-powered wireless sensors. IC Role / Device Role / Timing Role: Parameter and configuration store with individual sector locking to prevent accidental overwrite of calibration data. Use Value: Top/bottom block protect (TB) and complement protect (CMP) bits allow hierarchical write protection without software intervention. | Use Scenario: Retaining FDA-mandated device calibration logs, usage counters, and diagnostic history in portable ultrasound units. IC Role / Device Role / Timing Role: Secure, long-term non-volatile storage with tamper-evident write protection and unique ID for audit trail binding. Use Value: Three OTP-lockable security registers store cryptographic keys used to sign calibration records, satisfying IEC 62304 data integrity requirements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial NOR flash memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MX25L12833FZNI-10G | 3V supply (2.7–3.6V); no QPI mode; 80MHz max SPI clock; same 128M-bit density and SOIC-8 package | Requires level-shifting for 1.8V host; lacks QPI efficiency for XIP; lower throughput limits real-time code fetch | Select only if system already uses 3V I/O rails and does not require QPI or >80MHz performance |
| S25FL128SAGMFI000 | 1.8V supply; supports Octal DTR mode (up to 200MHz DDR); different status register map and security model | Higher bandwidth for video buffer loading; more complex initialization; Cypress-specific SFDP extensions | Prefer for bandwidth-intensive applications where Octal DTR is supported and Cypress toolchain is established |
Compared with MX25L12833FZNI-10G, W25Q128FWPIG TR delivers 30% higher SPI clock rate and QPI mode for deterministic XIP latency; versus S25FL128SAGMFI000, it offers simpler register compatibility and lower cost for standard Quad SPI implementations without Octal DTR requirement.
Availability
W25Q128FWPIG TR is available at Aetrix Electronics and suitable for industrial control, automotive telematics, and medical diagnostics requiring stable component supply, long-lifecycle support, and guaranteed traceable sourcing.
Supply support for W25Q128FWPIG TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Winbond Electronics is a Taiwan-based semiconductor company specializing in specialty memory solutions including NOR/NAND flash, RAM, and mobile DRAM since 1987.
The W25Q series targets embedded systems needing high-speed, low-voltage serial flash with robust security and flexible erase architecture - optimized for code storage, XIP, and firmware update resilience.
FAQ
What is the supply voltage range for W25Q128FWPIG TR?
The W25Q128FWPIG TR operates from 1.65 V to 1.95 V. This narrow 1.8V nominal range ensures compatibility with modern low-power microcontrollers and SoCs while maintaining sufficient noise margin. Operation outside this range may cause undefined behavior or permanent damage. Decoupling capacitance (≥100 nF ceramic) must be placed adjacent to the VCC pin per datasheet Section 9.4.
Does W25Q128FWPIG TR support execute-in-place (XIP) operation?
Yes, W25Q128FWPIG TR supports true XIP via Fast Read Quad I/O (EBh) and Continuous Read Mode, achieving up to 416MHz effective throughput. The 8-clock instruction overhead for address setup and wrap capability enable deterministic code fetch latency. XIP requires QE=1, proper bus timing alignment, and host controller support for Quad I/O instructions - verified in Winbond Application Note AN2017-03.
How is write protection implemented on W25Q128FWPIG TR?
W25Q128FWPIG TR implements layered write protection: hardware pins (/WP active-low when QE=0), volatile/non-volatile status register bits (BP2–BP0, TB, SEC, CMP, SRP0/SRP1), and OTP-locked security registers. Protection granularity ranges from individual 4KB sectors to full array. The /WP pin is disabled in Quad mode (QE=1), making register-based protection mandatory for secure configurations.
What package type is used by W25Q128FWPIG TR?
W25Q128FWPIG TR uses an 8-pin SOIC 208-mil package (Package Code S), with pinout matching Figure 1a in the datasheet. It has no exposed thermal pad. This package is RoHS-compliant, halogen-free, and rated for -40°C to +85°C operation. Footprint dimensions and soldering profiles follow JEDEC MS-012 standards.
Can W25Q128FWPIG TR be reset using a dedicated /RESET pin?
No - W25Q128FWPIG TR (SOIC-8 variant) does not have a dedicated /RESET pin. Reset functionality is multiplexed onto Pin 7 (/HOLD or /RESET), which operates as /HOLD by default. To use it as /RESET, the HOLD/RST bit (bit 7 of Status Register-3) must be set to '1' and QE=0. Hardware reset is only available on 16-pin SOIC (Package Code F) and TFBGA variants.
W25Q128FWPIG TR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Winbond Electronics Corporation
- Series:
- SpiFlash®
- Package/Case:
- 8-WDFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH - NOR
- Memory Size:
- 128Mbit
- Memory Organization:
- 16M x 8
- Memory Interface:
- SPI - Quad I/O, QPI
- Clock Frequency:
- 104 MHz
- Write Cycle Time - Word, Page:
- 60µs, 5ms
- Access Time:
- -
- Voltage - Supply:
- 1.65V ~ 1.95V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-WSON (6x5)
W25Q128FWPIG TR FAQ
1.How can I place an order for W25Q128FWPIG TR through Aetrix?
Please submit a Request for Quotation (RFQ) for W25Q128FWPIG TR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for W25Q128FWPIG TR reliable?
The price and inventory of W25Q128FWPIG TR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for W25Q128FWPIG TR is usually 5 days.
3.What payment methods are accepted for W25Q128FWPIG TR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for W25Q128FWPIG TR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for W25Q128FWPIG TR?
W25Q128FWPIG TR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your W25Q128FWPIG TR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for W25Q128FWPIG TR?
For technical support, including W25Q128FWPIG TR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your W25Q128FWPIG TR requirements.
6.How does Aetrix verify that W25Q128FWPIG TR is sourced from the original manufacturer or authorized distributors?
All W25Q128FWPIG TR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that W25Q128FWPIG TR meets industry standards.
7.What is the process for return or replacement of W25Q128FWPIG TR?
All W25Q128FWPIG TR units undergo pre-shipment inspection (PSI). If there is an issue with W25Q128FWPIG TR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The W25Q128FWPIG TR part is unused and in its original packaging.
Return procedure for W25Q128FWPIG TR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
W25Q128FWPIG TR Tags

-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology

-
AT21CS01-STUM10-T
Microchip Technology

-
AT24C02C-SSHM-T
Microchip Technology

-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics

-
AT24CS02-SSHM-T
Microchip Technology

-
93LC46BT-I/OT
Microchip Technology

-
AT24C04C-SSHM-T
Microchip Technology

-
24LC01BT-I/SN
Microchip Technology

-
24AA02UIDT-I/OT
Microchip Technology

-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
