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Winbond Electronics Corporation W25Q128JVBIM
- Part No.:
- W25Q128JVBIM
- Manufacturer:
- Winbond Electronics Corporation
- Category:
- Memory
- Package:
- 24-TBGA
- Datasheet:
-
W25Q128JVBIM.pdf
- Description:
- IC FLASH 128MBIT SPI 24TFBGA
- Quantity:
- Payment:
- Shipping:
Inventory:3,982
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Product details
Overview
W25Q128JVBIM from Winbond is a 128M-bit (16MB) serial NOR flash memory IC supporting Standard/Dual/Quad SPI, QPI, and DTR read modes. It operates from 2.7V to 3.6V, delivers up to 133MHz SPI clock (532MHz equivalent Quad I/O), features uniform 4KB sectors, 100K program-erase cycles, and 20-year data retention. It is used for XIP code execution, firmware storage, and parameter logging in industrial microcontroller systems.
For engineers reviewing the W25Q128JVBIM datasheet, W25Q128JVBIM pinout, W25Q128JVBIM application, or W25Q128JVBIM equivalent, key selection criteria include its dual-/quad-I/O timing compliance, /HOLD and /WP hardware protection, 8-pin SOIC 208-mil package compatibility, and JEDEC SFDP register support for auto-configuration.
Technical Context
The W25Q128JVBIM implements a quad-peripheral interface (QPI) with fixed 4-bit command/address/data width, enabling single-cycle instruction execution and eliminating opcode overhead. Its status register includes non-volatile Quad Enable (QE) bit (SR2[1]) required to activate IO2 (/WP) and IO3 (/HOLD) for Quad SPI operation.
It supports DTR (Double Transfer Rate) read modes - including DTR Fast Read (0Dh), DTR Quad I/O (EDh), and DTR Burst Read (0Eh) - where data is sampled on both clock edges, doubling effective throughput without increasing clock frequency. The device also integrates three 256-byte security registers with OTP lock bits (LB1–LB3) and a 64-bit unique ID.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 128 M-bit (16 MB), organized as 65,536 × 256-byte pages |
| Operating Voltage | 2.7 V to 3.6 V - compatible with standard 3.3 V logic rails and industrial supply tolerances |
| Max Clock Frequency | 133 MHz SPI - enables 66 MB/s continuous read via Quad I/O with wrap mode |
| Erase Granularity | Uniform 4 KB sectors (4,096 total), 32 KB blocks (2,048), 64 KB blocks (1,024), and full chip erase |
| Endurance & Retention | 100,000 program/erase cycles per sector; 20-year data retention at +85°C |
| Interface Modes | Standard SPI (4-wire), Dual SPI (2 I/O), Quad SPI (4 I/O), QPI (4-bit bus), and DTR variants of all |
| Security Features | 64-bit unique ID, three 256-byte OTP-lockable security registers, SFDP v1.6 compliant register |
Pinout & Package
W25Q128JVBIM uses the 8-pin SOIC 208-mil package (Package Code S), with exposed pad not present. Pin functions are defined per JEDEC-standard SPI/QPI protocol mapping and validated for industrial-grade operation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| /CS (Pin 1) | Chip Select Input | Active-low enable; places DO/IO pins in high-impedance state when deasserted; required to transition high→low before new instruction acceptance |
| DO / IO1 (Pin 2) | Data Output / Quad I/O Line 1 | Unidirectional output in Standard SPI; bidirectional I/O in Dual/Quad SPI and QPI; driven only when /CS is low |
| /WP / IO2 (Pin 3) | Write Protect Input / Quad I/O Line 2 | Hardware write lock for status register when QE=0; becomes IO2 in Quad mode (QE=1); active-low |
| GND (Pin 4) | Ground Reference | Primary return path for VCC and I/O signals; must be low-impedance connection for timing integrity |
| DI / IO0 (Pin 5) | Data Input / Quad I/O Line 0 | Unidirectional input in Standard SPI; bidirectional I/O in Dual/Quad SPI and QPI; samples on CLK rising edge |
| CLK (Pin 6) | Serial Clock Input | Synchronizes all SPI/QPI transfers; supports Mode 0 and Mode 3; max 133 MHz rated |
| /HOLD / IO3 (Pin 7) | Hold Input / Quad I/O Line 3 | Pauses ongoing read/write when asserted low during /CS active; becomes IO3 in Quad mode (QE=1); active-low |
| VCC (Pin 8) | Power Supply | Single 2.7–3.6 V supply; supports <1 µA typical power-down current when /CS high and no internal operation pending |
Key Features
| Feature | Design Value |
|---|---|
| Continuous Read with Wrap | Enables true XIP execution with ≤8-clock instruction overhead and configurable 8/16/32/64-byte burst wrap boundaries |
| DTR Read Support | Doubles data rate per clock cycle in Fast Read, Quad I/O, and Burst Read modes (e.g., 0Dh, EDh, 0Eh) without raising clock frequency |
| Flexible Hardware Protection | /WP and /HOLD pins retain dedicated function in Standard/Dual SPI; configurable top/bottom/sector-level lock via status register BP/TB/SEC bits |
| QPI Mode Efficiency | Reduces instruction overhead by encoding commands, addresses, and data in fixed 4-bit nibbles - eliminates opcode byte requirement |
| Industrial Temperature Range | Rated for –40°C to +85°C operation with guaranteed timing and endurance across full voltage range |
Applications
| Boot Firmware Storage | Real-Time Parameter Logging |
|---|---|
Use Scenario: Storing boot loader and application firmware for ARM Cortex-M4/M7 microcontrollers in factory automation controllers. IC Role / Device Role / Timing Role: Non-volatile code storage with XIP-capable Quad SPI interface; provides deterministic 133 MHz clock-aligned fetch latency. Use Value: Eliminates external RAM copy step during boot; reduces BOM count and PCB footprint versus parallel NOR flash. | Use Scenario: Recording sensor calibration coefficients, runtime fault logs, and configuration history in medical diagnostic equipment. IC Role / Device Role / Timing Role: Parameter archive with atomic 4 KB sector erase; supports frequent small writes using wear-leveling-aware firmware. Use Value: Enables field-updatable calibration without full firmware reflash; leverages 100K-cycle endurance for >10-year service life. |
| Firmware Over-the-Air (FOTA) Update | Secure Boot Key Storage |
Use Scenario: Holding dual firmware images (active + candidate) and metadata for fail-safe OTA updates in smart grid gateways. IC Role / Device Role / Timing Role: Dual-image partitioning with independent 4 KB sector locking; supports erase-suspend/resume during power-loss events. Use Value: Guarantees atomic image swap and rollback capability; prevents bricking during interrupted updates. | Use Scenario: Storing cryptographic keys and root-of-trust certificates in industrial IoT edge nodes requiring secure boot validation. IC Role / Device Role / Timing Role: Tamper-resistant key vault using OTP-locked security registers (LB1–LB3) and 64-bit unique ID for device binding. Use Value: Prevents key extraction via readout; enforces hardware-rooted identity without external secure element. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial NOR flash applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MX25L12833FZC-10G | 128 M-bit, 104 MHz max clock, no DTR support, lacks QPI mode, supports only Standard/Dual/Quad SPI | Lower peak bandwidth (52 MB/s vs 66 MB/s); no DTR timing margin for high-speed controllers | Select when DTR or QPI is unused and cost sensitivity outweighs timing headroom needs. |
| S25FL128SAGMFI000 | 128 M-bit, 133 MHz clock, supports DTR and QPI, but requires separate /RESET pin (16-pin SOIC only); no /HOLD pin in 8-pin variant | Requires PCB layout change for /RESET routing; lacks /HOLD functionality in space-constrained 8-pin designs | Select when hardware reset independence is mandatory and board real estate allows 16-pin footprint. |
Compared with MX25L12833FZC-10G and S25FL128SAGMFI000, W25Q128JVBIM uniquely combines DTR+QPI in an 8-pin SOIC package with integrated /HOLD and /WP - enabling highest bandwidth and lowest pin count for industrial XIP and FOTA use cases.
Availability
W25Q128JVBIM is available at Aetrix Electronics and suitable for industrial control systems, medical diagnostics equipment, and smart energy metering requiring stable component supply across extended temperature ranges and long product lifecycles.
Supply support for W25Q128JVBIM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Winbond Electronics is a Taiwan-based semiconductor company specializing in specialty memory solutions, including serial NOR/NAND flash, RAM, and mobile DRAM.
The W25Q series targets high-reliability embedded applications demanding fast read performance, flexible protection, and industrial-grade reliability - specifically designed for code storage, XIP execution, and secure firmware update in resource-constrained systems.
FAQ
What is the package type and pin count of W25Q128JVBIM?
W25Q128JVBIM uses an 8-pin SOIC 208-mil package (Package Code S), with pinout matching JEDEC-standard SPI/QPI interface definitions. It does not include a dedicated /RESET pin - the /HOLD pin (Pin 7) serves dual function and can be configured via Status Register for reset behavior only in specific package variants; W25Q128JVBIM implements /HOLD exclusively.
Does W25Q128JVBIM support Quad SPI and QPI modes?
Yes, W25Q128JVBIM supports both Quad SPI and QPI modes. Quad SPI requires setting the Quad Enable (QE) bit in Status Register-2; QPI mode is entered via instruction 38h and exited via FFh. Both modes utilize IO0–IO3 (Pins 5, 2, 3, 7) and deliver up to 532 MHz equivalent bandwidth at 133 MHz clock.
What is the maximum clock frequency and corresponding data rate for W25Q128JVBIM?
W25Q128JVBIM supports up to 133 MHz SPI clock frequency. In Quad I/O Fast Read mode, this yields a 532 MHz equivalent data rate and 66 MB/s continuous transfer rate. DTR modes double sampling per clock edge, maintaining full throughput without increasing clock speed.
How does hardware write protection work on W25Q128JVBIM?
W25Q128JVBIM implements dual-layer hardware write protection: the /WP pin (Pin 3) disables status register writes when asserted low, and Block Protect (BP2–BP0), Top/Bottom (TB), and Sector Protect (SEC) bits in Status Registers provide granular array locking. These settings persist across power cycles when written non-volatily.
Is W25Q128JVBIM suitable for execute-in-place (XIP) applications?
Yes, W25Q128JVBIM is explicitly designed for XIP operation. Its Continuous Read mode with ≤8-clock instruction overhead, Quad I/O and QPI support, and DTR timing enable deterministic code fetch directly from flash - verified in industrial microcontroller reference designs targeting Cortex-M and RISC-V cores.
W25Q128JVBIM Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Winbond Electronics Corporation
- Series:
- SpiFlash®
- Package/Case:
- 24-TBGA
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH - NOR
- Memory Size:
- 128Mbit
- Memory Organization:
- 16M x 8
- Memory Interface:
- SPI - Quad I/O, QPI, DTR
- Clock Frequency:
- 133 MHz
- Write Cycle Time - Word, Page:
- 3ms
- Access Time:
- -
- Voltage - Supply:
- 2.7V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 24-TFBGA (6x8)
W25Q128JVBIM FAQ
1.How can I place an order for W25Q128JVBIM through Aetrix?
Please submit a Request for Quotation (RFQ) for W25Q128JVBIM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for W25Q128JVBIM reliable?
The price and inventory of W25Q128JVBIM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for W25Q128JVBIM is usually 5 days.
3.What payment methods are accepted for W25Q128JVBIM?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for W25Q128JVBIM transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for W25Q128JVBIM?
W25Q128JVBIM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your W25Q128JVBIM order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for W25Q128JVBIM?
For technical support, including W25Q128JVBIM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your W25Q128JVBIM requirements.
6.How does Aetrix verify that W25Q128JVBIM is sourced from the original manufacturer or authorized distributors?
All W25Q128JVBIM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that W25Q128JVBIM meets industry standards.
7.What is the process for return or replacement of W25Q128JVBIM?
All W25Q128JVBIM units undergo pre-shipment inspection (PSI). If there is an issue with W25Q128JVBIM, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The W25Q128JVBIM part is unused and in its original packaging.
Return procedure for W25Q128JVBIM:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
W25Q128JVBIM Tags
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