Winbond Electronics Corporation W25Q128JVBIQ
- Part No.:
- W25Q128JVBIQ
- Manufacturer:
- Winbond Electronics Corporation
- Category:
- Memory
- Package:
- 24-TBGA
- Datasheet:
-
W25Q128JVBIQ.pdf
- Description:
- IC FLASH 128MBIT SPI 24TFBGA
- Quantity:
- Payment:

- Shipping:

Inventory:3,781
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
W25Q128JVBIQ from Winbond is a 128M-bit (16MB) serial NOR flash memory IC supporting Standard, Dual, and Quad SPI interfaces with 133MHz clock rate, 4KB uniform sector architecture, and hardware write protection via /WP and /HOLD pins - used for code storage, XIP execution, and firmware parameter retention in industrial microcontroller systems.
For engineers reviewing the W25Q128JVBIQ datasheet, W25Q128JVBIQ pinout, W25Q128JVBIQ application, or W25Q128JVBIQ equivalent, key selection considerations include Quad I/O enable (QE bit), 2.7–3.6V single-supply operation, -40°C to +105°C extended temperature grade, and compatibility with JEDEC SFDP and 64-bit unique ID for secure boot and device authentication.
Technical Context
The W25Q128JVBIQ implements a flexible SPI command set including Standard (DI/DO), Dual (IO0/IO1), and Quad (IO0–IO3) modes, with Quad operation enabled only when the non-volatile QE bit in Status Register-2 is set. Its internal architecture features a 256-byte page buffer, 4,096 erasable 4KB sectors, and three 256-byte one-time-programmable security registers.
It supports erase/program suspend/resume, continuous read with wrap (8/16/32/64-byte), and hardware reset via dedicated /RESET pin (available in TFBGA and SOIC-16 packages). The /HOLD pin functions as IO3 in Quad mode, and /WP serves dual role as IO2 when QE=1 - requiring careful pin mapping during layout.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 128 M-bit (16 MB), organized as 65,536 × 256-byte pages |
| Interface Support | Standard/Dual/Quad SPI with up to 133 MHz CLK; 532 MHz effective Quad I/O throughput |
| Operating Voltage | 2.7 V to 3.6 V - compatible with 3.3 V logic families without level shifting |
| Temperature Range | -40°C to +105°C - qualified for Industrial Plus grade applications |
| Erase/Program Endurance | 100,000 cycles per sector - supports frequent firmware updates in field-deployed devices |
| Data Retention | 20 years at +85°C - ensures long-term reliability in unpowered storage |
| Security Features | 64-bit unique ID, SFDP register, three 256-byte OTP security registers, and configurable BP/TB/SEC lock bits |
Pinout & Package
W25Q128JVBIQ is packaged in an 8-pin SOIC 208-mil (Package Code S) with exposed pad not present; pin 1 is /CS, pin 2 is DO (IO1), pin 3 is /WP (IO2), pin 4 is GND, pin 5 is DI (IO0), pin 6 is CLK, pin 7 is /HOLD (IO3), and pin 8 is VCC. /HOLD functions as IO3 in Quad mode; /WP becomes IO2 when QE=1.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| /CS (Pin 1) | Chip Select Input | Active-low enable; high-impedance DO output and standby current (<1 µA) when deasserted |
| DO (IO1) (Pin 2) | Serial Data Output / Bidirectional I/O | Unidirectional output in Standard SPI; bidirectional IO1 in Dual/Quad modes - requires QE=1 for Quad use |
| /WP (IO2) (Pin 3) | Write Protect Input / Bidirectional I/O | Hardware lock for status register; becomes IO2 in Quad mode when QE=1 - cannot be used for protection simultaneously |
| GND (Pin 4) | Ground Reference | Primary return path for VCC and all I/O signals; must be low-impedance for stable SPI timing |
| DI (IO0) (Pin 5) | Serial Data Input / Bidirectional I/O | Unidirectional input in Standard SPI; bidirectional IO0 in Dual/Quad modes - required for all instruction transfers |
| CLK (Pin 6) | Serial Clock Input | Edge-triggered timing reference; supports Mode 0 and Mode 3; max 133 MHz for reliable setup/hold margins |
| /HOLD (IO3) (Pin 7) | Hold Input / Bidirectional I/O | Pauses ongoing read/write; becomes IO3 in Quad mode - function disabled when QE=1 |
| VCC (Pin 8) | Power Supply | Single 2.7–3.6 V supply; decoupling capacitor (0.1 µF) required within 5 mm of pin for noise immunity |
Key Features
| Feature | Design Value |
|---|---|
| Quad SPI Enable (QE bit) | Non-volatile bit in Status Register-2 that reassigns /WP and /HOLD to IO2/IO3 - enables 4-line data transfer without external logic |
| Continuous Read with Wrap | Supports 8/16/32/64-byte burst wrap modes - reduces address overhead and enables true XIP execution from flash |
| Erase/Program Suspend | Allows pausing active erase or program operations to service higher-priority reads - critical for real-time firmware update scenarios |
| Individual Sector Lock | Per-sector (4KB) lock/unlock via 32h/39h instructions - enables fine-grained protection of bootloader, calibration data, or user configuration |
| JEDEC SFDP Compliance | Standard Flash Discovery Parameter table accessible via 5Ah command - enables automatic driver configuration in Linux/Baremetal bootloaders |
Applications
| Industrial PLC Firmware Storage | Automotive ADAS Bootloader |
|---|---|
Use Scenario: Storing firmware images and runtime parameters in programmable logic controllers operating in harsh factory environments with wide temperature swings. IC Role / Device Role / Timing Role: Non-volatile code storage and XIP execution source - directly mapped into MCU address space via QSPI controller. Use Value: 4KB uniform sectors allow independent update of control logic vs. safety-critical boot code; 100K endurance supports over-the-air firmware patches across 10+ years of service life. |
Use Scenario: Hosting boot firmware and sensor calibration tables in automotive Advanced Driver Assistance Systems with ASIL-B functional safety requirements. IC Role / Device Role / Timing Role: Secure boot root-of-trust component - verified via 64-bit unique ID and SFDP-managed read latency tuning. Use Value: Three OTP security registers store cryptographic keys; hardware write-protection on boot sector prevents unauthorized modification during vehicle operation. |
| Medical IoT Edge Device | Smart Energy Meter Firmware |
Use Scenario: Persistent storage of patient data logs and algorithm updates in battery-powered portable diagnostic equipment. IC Role / Device Role / Timing Role: Low-power data logger and firmware repository - leverages <1 µA power-down current and fast wake-up from /CS assertion. Use Value: 20-year data retention ensures integrity of stored clinical records; Quad SPI read speeds (>66 MB/s) accelerate firmware validation before execution. |
Use Scenario: Storing tariff tables, communication stack binaries, and tamper-event logs in utility-grade smart meters deployed outdoors for >15 years. IC Role / Device Role / Timing Role: Field-upgradable firmware and secure parameter vault - protected by top/bottom block lock and complement array protection. Use Value: Hardware /WP and /HOLD pins provide physical layer security against glitch-based attacks; -40°C to +105°C rating ensures operation in unheated meter enclosures. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial NOR flash memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MX25L12833FZNI-08G | 128M-bit, 104MHz max CLK, no hardware /RESET pin, supports only Standard/Dual SPI (no Quad I/O) | Lacks Quad SPI and QE bit - unsuitable for XIP or high-throughput code shadowing | Select only if system uses only Standard/Dual SPI and does not require 133MHz timing or 4-line data paths |
| S25FL128SAGMFIR00 | 128M-bit, 133MHz, Quad SPI, but requires external VIO supply (1.7–2.0V) for I/O voltage scaling | Additional power rail complexity; incompatible with single 3.3V-only designs | Choose only when mixed-voltage SoC interface demands separate I/O voltage control |
Compared with MX25L12833FZNI-08G and S25FL128SAGMFIR00, W25Q128JVBIQ delivers full Quad SPI capability at 133MHz with single 3.3V supply and integrated hardware write protection - making it optimal for cost-sensitive, high-performance embedded systems requiring XIP and secure firmware storage without auxiliary power rails or external level shifters.
Availability
W25Q128JVBIQ is available at Aetrix Electronics and suitable for industrial automation, automotive telematics, medical edge devices, and smart energy metering requiring stable component supply across extended temperature and long product lifecycles.
Supply support for W25Q128JVBIQ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Winbond Electronics is a Taiwan-based semiconductor manufacturer specializing in specialty memory solutions, including serial NOR/NAND flash, RAM, and trusted computing components.
The W25Q series was designed for high-reliability embedded systems requiring fast, secure, and flexible code and data storage - with emphasis on industrial, automotive, and medical applications demanding extended temperature operation and robust security features.
FAQ
What is the maximum SPI clock frequency supported by W25Q128JVBIQ?
W25Q128JVBIQ supports up to 133 MHz for Standard and Dual SPI operation, and up to 133 MHz for Quad SPI clock input - enabling effective data rates of 266 Mbps (Dual) and 532 Mbps (Quad) using Fast Read Dual/Quad I/O instructions. This timing is validated across the full -40°C to +105°C operating range and requires proper PCB layout with controlled impedance and minimal stub length.
Does W25Q128JVBIQ support hardware reset, and which package types include the /RESET pin?
Yes, W25Q128JVBIQ supports hardware reset via a dedicated /RESET pin, but this pin is only present in SOIC-16 (Package Code F) and TFBGA (Package Codes B/C) variants - not in the 8-pin SOIC 208-mil (Package Code S) used for W25Q128JVBIQ. For W25Q128JVBIQ, software reset using 66h + 99h commands is the only supported reset method.
How is Quad SPI mode enabled on W25Q128JVBIQ, and what happens to the /WP and /HOLD pins?
Quad SPI mode on W25Q128JVBIQ is enabled by setting the non-volatile Quad Enable (QE) bit in Status Register-2 (SR2) using instruction 31h. When QE=1, the /WP pin becomes IO2 and the /HOLD pin becomes IO3 - both lose their hardware protection functions and operate exclusively as bidirectional data lines. This reassignment is permanent until cleared via SR2 write.
What is the sector erase granularity of W25Q128JVBIQ, and why does it matter for firmware updates?
W25Q128JVBIQ provides uniform 4KB sector erase granularity across its entire 16MB array (4,096 sectors total). This allows precise erasure of individual firmware modules - such as bootloader, application, or configuration sections - without disturbing adjacent code or data. It minimizes update time and wear on unrelated memory regions, extending overall flash lifetime in field-upgradable systems.
Can W25Q128JVBIQ be used for execute-in-place (XIP) operation, and what conditions must be met?
Yes, W25Q128JVBIQ supports true XIP operation via Fast Read Quad I/O (EBh) and Continuous Read with Wrap modes. To enable reliable XIP, the host MCU's QSPI controller must support Quad I/O mode, the QE bit must be set, and the system must ensure deterministic read latency - achievable using the device's built-in dummy cycle adjustment and SFDP register for automatic timing calibration.
W25Q128JVBIQ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Winbond Electronics Corporation
- Series:
- SpiFlash®
- Package/Case:
- 24-TBGA
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH - NOR
- Memory Size:
- 128Mbit
- Memory Organization:
- 16M x 8
- Memory Interface:
- SPI - Quad I/O, QPI
- Clock Frequency:
- 133 MHz
- Write Cycle Time - Word, Page:
- 3ms
- Access Time:
- -
- Voltage - Supply:
- 2.7V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 24-TFBGA (6x8)
W25Q128JVBIQ FAQ
1.How can I place an order for W25Q128JVBIQ through Aetrix?
Please submit a Request for Quotation (RFQ) for W25Q128JVBIQ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for W25Q128JVBIQ reliable?
The price and inventory of W25Q128JVBIQ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for W25Q128JVBIQ is usually 5 days.
3.What payment methods are accepted for W25Q128JVBIQ?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for W25Q128JVBIQ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for W25Q128JVBIQ?
W25Q128JVBIQ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your W25Q128JVBIQ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for W25Q128JVBIQ?
For technical support, including W25Q128JVBIQ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your W25Q128JVBIQ requirements.
6.How does Aetrix verify that W25Q128JVBIQ is sourced from the original manufacturer or authorized distributors?
All W25Q128JVBIQ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that W25Q128JVBIQ meets industry standards.
7.What is the process for return or replacement of W25Q128JVBIQ?
All W25Q128JVBIQ units undergo pre-shipment inspection (PSI). If there is an issue with W25Q128JVBIQ, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The W25Q128JVBIQ part is unused and in its original packaging.
Return procedure for W25Q128JVBIQ:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
W25Q128JVBIQ Tags

-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology

-
AT21CS01-STUM10-T
Microchip Technology

-
AT24C02C-SSHM-T
Microchip Technology

-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics

-
AT24CS02-SSHM-T
Microchip Technology

-
93LC46BT-I/OT
Microchip Technology

-
AT24C04C-SSHM-T
Microchip Technology

-
24LC01BT-I/SN
Microchip Technology

-
24AA02UIDT-I/OT
Microchip Technology

-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

