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Winbond Electronics Corporation W25Q128JVBJM TR
- Part No.:
- W25Q128JVBJM TR
- Manufacturer:
- Winbond Electronics Corporation
- Category:
- Memory
- Package:
- 24-TBGA
- Datasheet:
-
W25Q128JVBJM TR.pdf
- Description:
- IC FLASH 128MBIT SPI 24TFBGA
- Quantity:
- Payment:
- Shipping:
Inventory:3,768
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Product details
Overview
W25Q128JVBJM TR from Winbond is a 128M-bit (16MB) serial NOR flash memory IC supporting Standard/Dual/Quad SPI, QPI, and DTR read modes. It operates from 2.7V to 3.6V, delivers up to 133MHz SPI clock (532MHz equivalent Quad I/O), features 4KB uniform sectors, 100K program-erase cycles per sector, and 20-year data retention. It serves as nonvolatile code storage and XIP execution memory in microcontroller-based embedded systems.
For engineers reviewing the W25Q128JVBJM TR datasheet, W25Q128JVBJM TR pinout, W25Q128JVBJM TR application, or W25Q128JVBJM TR equivalent, key selection criteria include Quad Enable (QE) bit configuration for IO2/IO3 remapping, /HOLD vs /RESET pin availability by package, DTR timing compliance, sector protection granularity, and SFDP register support for auto-configuration.
Technical Context
The W25Q128JVBJM TR implements a multi-mode serial interface with configurable I/O count: Standard SPI uses DI/DO unidirectionally; Dual/Quad SPI and QPI use IO0–IO3 bidirectionally after QE bit (Status Register-2, bit 1) is set. Its command set includes DTR Fast Read (0Dh/BDh/EDh) requiring precise setup/hold timing on CLK and /CS relative to data edges.
Internal architecture includes a 256-byte page buffer, uniform 4KB sector erase capability, programmable block protection (BP2–BP0, TB, SEC, CMP), volatile/non-volatile status register bits, and three 256-byte one-time-programmable security registers. The device supports hardware reset via dedicated /RESET pin only in SOIC-16 and TFBGA packages-not in the 8-pin SOIC or WSON variants.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 128 M-bit (16 MB), organized as 65,536 × 256-byte pages |
| Operating Voltage | 2.7 V to 3.6 V - compatible with 3.3 V logic systems without level shifting |
| SPI Clock Frequency | Up to 133 MHz - enables 66 MB/s continuous read throughput in Quad I/O mode |
| Erase Granularity | 4 KB sectors, 32 KB blocks, 64 KB blocks - allows fine-grained firmware partitioning and OTA update safety |
| Endurance & Retention | 100,000 program/erase cycles per sector; 20-year data retention at +85°C |
| Interface Modes | Standard/Dual/Quad SPI, QPI, and DTR - selectable via instruction set; QE bit controls IO2/IO3 function |
| Security Features | 64-bit unique ID, SFDP register, three 256-byte OTP security registers, and configurable sector lock/unlock |
Pinout & Package
W25Q128JVBJM TR is supplied in an 8-pin SOIC 208-mil package (Package Code S), with pins arranged as follows:
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 /CS | Chip Select Input | Active-low enable; high-impedance DO during deselect; must transition high→low post-power-up to accept commands |
| 2 DO (IO1) | Data Output / I/O1 | Unidirectional output in Standard SPI; bidirectional I/O in Dual/Quad SPI/QPI after QE=1 |
| 3 /WP (IO2) | Write Protect Input / I/O2 | Hardware write-protection control when QE=0; becomes IO2 in Quad mode (QE=1) |
| 4 GND | Ground Reference | Primary return path for VCC and all I/O signals; requires low-impedance PCB connection |
| 5 DI (IO0) | Data Input / I/O0 | Unidirectional input in Standard SPI; bidirectional I/O in Dual/Quad SPI/QPI after QE=1 |
| 6 CLK | Serial Clock Input | Edge-triggered timing reference; supports SPI Mode 0 and Mode 3; DTR requires strict tDSU/tDH compliance |
| 7 /HOLD or /RESET (IO3) | Hold/Reset Input / I/O3 | HOLD active-low pause function when QE=0; not available as /RESET in 8-pin SOIC - no dedicated reset pin |
| 8 VCC | Power Supply | Single 2.7–3.6 V supply; typical power-down current <1 µA enables ultra-low-power system sleep states |
Key Features
| Feature | Design Value |
|---|---|
| Quad Peripheral Interface (QPI) | Reduces instruction overhead to 1-cycle per byte, enabling true execute-in-place (XIP) from flash without RAM copy |
| DTR Read Support | Enables double-data-rate sampling on CLK edges - doubles effective bandwidth without increasing clock frequency |
| Uniform 4KB Sector Architecture | Allows independent firmware image partitioning, secure boot region isolation, and atomic OTA update rollback |
| Volatile/Non-Volatile Status Register Bits | Enables runtime reconfiguration of protection (BP, TB, SEC) and driver strength (DRV1/DRV0) without permanent commitment |
| Discoverable Parameters (SFDP) | Provides standardized JEDEC-defined register for automatic controller detection of timing, density, and feature set |
Applications
| Industrial HMI Display Firmware Storage | Automotive ADAS Camera Boot Memory |
|---|---|
Use Scenario: Storing GUI assets, font libraries, and firmware images for touch-enabled industrial panels operating in -40°C to +85°C environments. IC Role / Device Role / Timing Role: Nonvolatile code and asset storage with XIP-capable Quad SPI interface to reduce external RAM footprint and boot latency. Use Value: 4KB sector erase enables incremental firmware patching; 100K endurance ensures >10 years of field updates under daily calibration cycles. | Use Scenario: Holding boot code and sensor calibration data for automotive-grade camera modules requiring AEC-Q100 compliance and functional safety support. IC Role / Device Role / Timing Role: Primary boot memory accessed via QPI at 133 MHz to meet ASIL-B boot time requirements (<500 ms). Use Value: SFDP register allows automatic timing parameter loading by host SoC; security registers store encrypted calibration keys with OTP locking. |
| Medical IoT Sensor Node Configuration | Networking Equipment FPGA Bitstream Storage |
Use Scenario: Storing device-specific calibration coefficients, patient history templates, and regulatory-compliant audit logs in portable diagnostic sensors. IC Role / Device Role / Timing Role: Parameter and data log storage with hardware write protection (/WP pin) and individual sector lock (36h/39h instructions). Use Value: Top/bottom block protect (TB bit) isolates factory-calibrated regions from field-modifiable user data zones. | Use Scenario: Storing compressed FPGA configuration bitstreams for telecom switches requiring fast, reliable reconfiguration after power loss. IC Role / Device Role / Timing Role: High-throughput configuration memory accessed via DTR Quad I/O to achieve sub-second FPGA startup. Use Value: 66 MB/s continuous read rate reduces boot time by >40% vs legacy Parallel NOR; 24-ball TFBGA variant supports high-density BGA routing. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial NOR flash memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MX25L12833FZNI-08G | 128 M-bit, 3.3 V, supports DTR but lacks QPI mode; max SPI clock 104 MHz; no SFDP register | Lower bandwidth; no auto-configuration; suitable for cost-sensitive designs without XIP or dynamic timing adaptation | Select when QPI and SFDP are unnecessary and legacy controller compatibility is prioritized over performance |
| S25FL128SAGMFI000 | 128 M-bit, 3.0 V min, supports Octal DTR (x8), 166 MHz clock; includes ECC and sector lockdown | Higher reliability features for mission-critical storage; larger footprint (16-pin SOIC); higher cost | Select when built-in ECC, enhanced security lockdown, or future-proof octal interface scalability is required |
Compared with MX25L12833FZNI-08G and S25FL128SAGMFI000, the W25Q128JVBJM TR uniquely balances QPI-enabled XIP efficiency, DTR bandwidth, SFDP auto-negotiation, and industrial temperature support in an 8-pin SOIC footprint - making it optimal for space-constrained, performance-aware embedded boot and code storage.
Availability
W25Q128JVBJM TR is available at Aetrix Electronics and suitable for industrial HMI, automotive camera modules, medical sensor nodes, and networking equipment requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for W25Q128JVBJM TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Winbond Electronics is a Taiwan-based semiconductor company specializing in specialty DRAM, mobile DRAM, and serial flash memory solutions for industrial, automotive, and consumer markets.
The W25Q series was designed specifically for high-performance, low-power embedded systems requiring robust code storage, XIP execution, and flexible security - targeting applications where reliability, density, and interface versatility outweigh raw cost minimization.
FAQ
What is the package type and pin count of the W25Q128JVBJM TR?
The W25Q128JVBJM TR is packaged in an 8-pin SOIC 208-mil (Package Code S) with standard /CS, CLK, DI, DO, /WP, /HOLD, VCC, and GND terminals. It does not include a dedicated /RESET pin - that function is only available in SOIC-16 and TFBGA variants of the W25Q128JV family.
Does the W25Q128JVBJM TR support Quad SPI and QPI modes?
Yes, the W25Q128JVBJM TR supports both Quad SPI and QPI modes. Activation requires setting the Quad Enable (QE) bit in Status Register-2. Once enabled, IO2 (/WP) and IO3 (/HOLD) become functional as bidirectional data lines, enabling 4-bit-wide transfers and reduced instruction overhead in QPI mode.
What is the maximum clock frequency supported by the W25Q128JVBJM TR in DTR mode?
The W25Q128JVBJM TR supports DTR (Double Transfer Rate) read operations at up to 133 MHz SPI clock frequency, achieving effective data rates of 266 Mbps (Dual I/O) and 532 Mbps (Quad I/O). DTR timing requires strict adherence to tDSU and tDH specifications per the datasheet's AC characteristics table.
How many program-erase cycles does the W25Q128JVBJM TR guarantee per sector?
The W25Q128JVBJM TR guarantees a minimum of 100,000 program-erase cycles per 4KB sector, with data retention exceeding 20 years at +85°C. This endurance rating applies to all sectors across the full operating temperature range (-40°C to +85°C) and is validated per JEDEC standards.
Is the W25Q128JVBJM TR compatible with SFDP (Serial Flash Discoverable Parameters)?
Yes, the W25Q128JVBJM TR implements the JEDEC JESD216 standard SFDP register, accessible via instruction 5Ah. This allows host controllers to automatically detect memory geometry, timing parameters, erase block sizes, and supported instruction sets - eliminating hardcoded configuration in bootloader firmware.
W25Q128JVBJM TR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Winbond Electronics Corporation
- Series:
- SpiFlash®
- Package/Case:
- 24-TBGA
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH - NOR
- Memory Size:
- 128Mbit
- Memory Organization:
- 16M x 8
- Memory Interface:
- SPI - Quad I/O, QPI, DTR
- Clock Frequency:
- 133 MHz
- Write Cycle Time - Word, Page:
- 3ms
- Access Time:
- -
- Voltage - Supply:
- 2.7V ~ 3.6V
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 24-TFBGA (6x8)
W25Q128JVBJM TR FAQ
1.How can I place an order for W25Q128JVBJM TR through Aetrix?
Please submit a Request for Quotation (RFQ) for W25Q128JVBJM TR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for W25Q128JVBJM TR reliable?
The price and inventory of W25Q128JVBJM TR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for W25Q128JVBJM TR is usually 5 days.
3.What payment methods are accepted for W25Q128JVBJM TR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for W25Q128JVBJM TR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for W25Q128JVBJM TR?
W25Q128JVBJM TR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your W25Q128JVBJM TR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for W25Q128JVBJM TR?
For technical support, including W25Q128JVBJM TR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your W25Q128JVBJM TR requirements.
6.How does Aetrix verify that W25Q128JVBJM TR is sourced from the original manufacturer or authorized distributors?
All W25Q128JVBJM TR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that W25Q128JVBJM TR meets industry standards.
7.What is the process for return or replacement of W25Q128JVBJM TR?
All W25Q128JVBJM TR units undergo pre-shipment inspection (PSI). If there is an issue with W25Q128JVBJM TR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The W25Q128JVBJM TR part is unused and in its original packaging.
Return procedure for W25Q128JVBJM TR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
W25Q128JVBJM TR Tags
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M24C02-WMN6TP
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AT24C02C-XHM-T
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AT24CS02-SSHM-T
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AT24C04C-SSHM-T
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