Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Memory > Memory

Winbond Electronics Corporation W25Q128JVBJQ

Name: W25Q128JVBJQ
Brand: Winbond Electronics Corporation
SKU: W25Q128JVBJQ
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: W25Q128JVBJQ

Manufacturer:: Winbond Electronics Corporation

Category:: Memory

Package:: 24-TBGA

Datasheet:: W25Q128JVBJQ.pdf

Description:: IC FLASH 128MBIT SPI 24TFBGA

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:2,994

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

W25Q128JVBJQ from Winbond is a 128M-bit (16MB) serial NOR flash memory IC supporting Standard/Dual/Quad SPI interfaces, operating at 2.7–3.6V, with 133MHz max clock and 66MB/s continuous read throughput. It features uniform 4KB sectors, 100K program-erase cycles per sector, and 20+ year data retention - deployed in embedded boot code storage, firmware update partitions, and XIP-capable microcontroller systems.

For engineers reviewing the W25Q128JVBJQ datasheet, W25Q128JVBJQ pinout, W25Q128JVBJQ application, or W25Q128JVBJQ equivalent, key selection criteria include Quad SPI enable (QE bit), /HOLD vs /RESET pin availability by package, 4KB sector granularity for parameter storage, and hardware write protection via /WP and status register bits.

Technical Context

The W25Q128JVBJQ implements a SPI-compatible command set with three instruction modes: Standard (DI/DO), Dual (IO0/IO1), and Quad (IO0–IO3), where Quad mode requires non-volatile QE=1 in Status Register-2. Its internal architecture includes a 256-byte page buffer, sector/block erase logic, and three 256-byte security registers with OTP lock capability.

It supports JEDEC-standard device ID (9Fh), SFDP register (5Ah), and 64-bit unique serial number (4Bh). Write protection combines volatile/non-volatile status bits (BP2–BP0, TB, SEC, CMP, SRP), hardware /WP pin control, and power supply lock-down - all configurable without external components.

Key Specifications

Parameter	Value and Actual Design Meaning
Memory Density	128 M-bit (16 MB), organized as 65,536 × 256-byte pages
Interface Support	Standard SPI (CLK, /CS, DI, DO), Dual SPI (IO0/IO1), Quad SPI (IO0–IO3) with QE bit enable
Max Clock Frequency	133 MHz single I/O; 266 MHz equivalent dual I/O; 532 MHz equivalent quad I/O
Erase Granularity	Uniform 4 KB sectors (4,096 total), 32 KB blocks (2,048), 64 KB blocks (256), full chip erase
Endurance & Retention	≥100,000 program-erase cycles per sector; >20 years data retention at +85°C
Supply Voltage	2.7 V to 3.6 V; typical power-down current <1 µA
Operating Temperature	–40°C to +85°C (Industrial Grade); –40°C to +105°C (Industrial Plus Grade)

Pinout & Package

W25Q128JVBJQ uses the 8-pin SOIC 208-mil package (Package Code S), with no dedicated /RESET pin - /HOLD functionality shares Pin 7. All pins support standard/dual SPI; Quad SPI repurposes /WP (Pin 3) as IO2 and /HOLD (Pin 7) as IO3 when QE=1.

Pin/Terminal	Circuit Role	Design Meaning
1 /CS	Chip Select Input	Active-low enable; high-impedance DO during deselect; required high-to-low transition before new instruction acceptance
2 DO (IO1)	Data Output / Bidirectional I/O	Unidirectional output in Standard SPI; bidirectional IO1 in Dual/Quad SPI; used for Fast Read instructions
3 /WP (IO2)	Write Protect Input / Bidirectional I/O	Hardware lock for status register writes; becomes IO2 in Quad SPI when QE=1; active-low
4 GND	Ground Reference	Primary return path for VCC and signal currents; must be low-impedance connection
5 DI (IO0)	Data Input / Bidirectional I/O	Unidirectional input in Standard SPI; bidirectional IO0 in Dual/Quad SPI; carries instructions, addresses, data
6 CLK	Serial Clock Input	Edge-triggered timing source; supports SPI Mode 0 (CPOL=0, CPHA=0) and Mode 3 (CPOL=1, CPHA=1)
7 /HOLD (IO3)	Hold Input / Bidirectional I/O	Pauses ongoing read/write while /CS active; becomes IO3 in Quad SPI when QE=1; active-low
8 VCC	Power Supply	Single 2.7–3.6 V supply; decoupling capacitor (0.1 µF) required near pin

Key Features

Feature	Design Value
Quad SPI Enable (QE)	Non-volatile bit in Status Register-2 enabling IO2/IO3 for 4-line data transfer - essential for 532 MHz equivalent throughput
Erase/Program Suspend	75h/7Ah commands allow pausing long erase/program operations to service urgent reads - critical for real-time firmware updates
Individual Sector Lock	36h/39h/3Dh instructions provide per-sector write protection independent of BP bits - enables fine-grained secure parameter storage
Security Registers	Three 256-byte OTP-lockable registers for keys, certificates, or calibration data - protected by LB1–LB3 bits in Status Register-3
Continuous Read Wrap	77h command configures 8/16/32/64-byte wrap boundaries - eliminates address overhead for streaming audio/video buffers

Applications

Boot Code Storage	Firmware Over-the-Air (OTA) Update Partition
Use Scenario: Storing primary bootloader and application firmware for ARM Cortex-M or RISC-V microcontrollers. IC Role / Device Role / Timing Role: Non-volatile code storage with XIP support via Quad SPI Fast Read Quad I/O (EBh) at up to 532 MHz equivalent rate. Use Value: Enables direct execution from flash without RAM copy, reducing boot time and BOM cost while maintaining deterministic timing.	Use Scenario: Isolating a dedicated 2–4 MB partition for validated firmware images during wireless updates. IC Role / Device Role / Timing Role: Erase-protected, sector-level writable memory region managed by bootloader using 4KB sector erase (20h) and page program (02h). Use Value: Allows atomic firmware swap with rollback capability, leveraging individual sector lock (36h) to prevent partial writes during power loss.
Secure Configuration Storage	Audio/Video Buffering in Edge Devices
Use Scenario: Storing calibrated sensor offsets, network credentials, and device-specific keys in industrial gateways. IC Role / Device Role / Timing Role: Tamper-resistant storage using Security Registers (42h/48h) and OTP lock bits (LB1–LB3) in Status Register-3. Use Value: Prevents unauthorized readout or modification of sensitive data without physical access or OTP unlock sequence.	Use Scenario: Streaming compressed audio frames or video thumbnails in smart speakers or IP cameras. IC Role / Device Role / Timing Role: High-throughput sequential read buffer using Continuous Read Wrap (77h) with 64-byte boundary alignment. Use Value: Delivers sustained 66 MB/s throughput with zero address retransmission overhead - ideal for bursty media payloads.

Boot Code Storage

Firmware Over-the-Air (OTA) Update Partition

Use Scenario: Storing primary bootloader and application firmware for ARM Cortex-M or RISC-V microcontrollers.

IC Role / Device Role / Timing Role: Non-volatile code storage with XIP support via Quad SPI Fast Read Quad I/O (EBh) at up to 532 MHz equivalent rate.

Use Value: Enables direct execution from flash without RAM copy, reducing boot time and BOM cost while maintaining deterministic timing.

Use Scenario: Isolating a dedicated 2–4 MB partition for validated firmware images during wireless updates.

IC Role / Device Role / Timing Role: Erase-protected, sector-level writable memory region managed by bootloader using 4KB sector erase (20h) and page program (02h).

Use Value: Allows atomic firmware swap with rollback capability, leveraging individual sector lock (36h) to prevent partial writes during power loss.

Secure Configuration Storage

Audio/Video Buffering in Edge Devices

Use Scenario: Storing calibrated sensor offsets, network credentials, and device-specific keys in industrial gateways.

IC Role / Device Role / Timing Role: Tamper-resistant storage using Security Registers (42h/48h) and OTP lock bits (LB1–LB3) in Status Register-3.

Use Value: Prevents unauthorized readout or modification of sensitive data without physical access or OTP unlock sequence.

Use Scenario: Streaming compressed audio frames or video thumbnails in smart speakers or IP cameras.

IC Role / Device Role / Timing Role: High-throughput sequential read buffer using Continuous Read Wrap (77h) with 64-byte boundary alignment.

Use Value: Delivers sustained 66 MB/s throughput with zero address retransmission overhead - ideal for bursty media payloads.

Equivalent & Alternatives

The following parts are listed as comparable options for similar serial NOR flash applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
MX25L12833F	128 M-bit, 3V, supports Dual/Quad SPI but lacks Security Registers and SFDP; max clock 104 MHz	No OTP-locked security registers or discoverable parameters - unsuitable for secure credential storage	Choose when cost sensitivity outweighs security and advanced configuration needs
S25FL128S	128 M-bit, 3V, Quad SPI, 133 MHz, includes SFDP and 256-byte security register (1x), but no individual sector lock	Lacks 3×256-byte security registers and 36h/39h sector lock/unlock - limited secure partitioning capability	Prefer when single-key storage suffices and legacy Cypress toolchain integration is required

Compared with MX25L12833F and S25FL128S, the W25Q128JVBJQ uniquely delivers triple OTP-lockable security registers, individual sector lock commands, and full SFDP compliance - making it the only option among the three qualified for multi-domain secure firmware and parameter storage in industrial edge devices.

Availability

W25Q128JVBJQ is available at Aetrix Electronics and suitable for boot code storage, OTA firmware partitions, and secure configuration storage requiring stable component supply across industrial temperature grades and long product lifecycles.

Supply support for W25Q128JVBJQ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Winbond Electronics is a Taiwan-based semiconductor company specializing in specialty memory solutions, including SPI NOR/NAND flash, RAM, and mobile DRAM.

The W25Q series targets embedded systems needing high-speed, secure, and flexible serial flash - designed specifically for code execution (XIP), firmware updates, and parameter storage in space-constrained industrial and automotive applications.

FAQ

What is the package type and pin count of the W25Q128JVBJQ?

The W25Q128JVBJQ uses an 8-pin SOIC 208-mil package (Package Code S) with standard SPI pinout: /CS, DO (IO1), /WP (IO2), GND, DI (IO0), CLK, /HOLD (IO3), and VCC. It does not include a dedicated /RESET pin - that function is only available on SOIC-16 and TFBGA variants.

Does the W25Q128JVBJQ support Quad SPI operation, and how is it enabled?

Yes, the W25Q128JVBJQ supports Quad SPI via IO0–IO3. It requires setting the non-volatile Quad Enable (QE) bit in Status Register-2 using instruction 31h. Once enabled, /WP (Pin 3) becomes IO2 and /HOLD (Pin 7) becomes IO3 - confirmed in the official datasheet Section 4.2 and Figure 1a.

How many program-erase cycles does the W25Q128JVBJQ guarantee per sector?

The W25Q128JVBJQ guarantees a minimum of 100,000 program-erase cycles per 4KB sector, as specified in the "Features" section (page 4) and "Electrical Characteristics" (Section 9.6) of the March 2018 Revision F datasheet - validated under industrial-grade operating conditions.

Can the W25Q128JVBJQ store secure keys or certificates?

Yes, the W25Q128JVBJQ includes three 256-byte Security Registers accessible via instructions 42h (program), 48h (read), and 44h (erase), each protected by one-time-programmable (OTP) lock bits LB1–LB3 in Status Register-3 - enabling tamper-resistant storage of cryptographic keys or device certificates.

What is the maximum continuous read throughput of the W25Q128JVBJQ?

The W25Q128JVBJQ achieves up to 66 MB/s continuous read throughput using Fast Read Quad I/O (EBh) at 133 MHz clock, delivering 532 MHz equivalent bandwidth. This value is measured under standard load conditions and documented in the "Features" table (page 4) and AC Electrical Characteristics (Section 9.6).

W25Q128JVBJQ Specifications

Product attributes: Attribute value

Manufacturer:: Winbond Electronics Corporation

Series:: SpiFlash®

Package/Case:: 24-TBGA

Packaging:: Tube

Product Status:: Active

Programmable:: Not Verified

Memory Type:: Non-Volatile

Memory Format:: FLASH

Technology:: FLASH - NOR

Memory Size:: 128Mbit

Memory Organization:: 16M x 8

Memory Interface:: SPI - Quad I/O, QPI, DTR

Clock Frequency:: 133 MHz

Write Cycle Time - Word, Page:: 3ms

Access Time:: -

Voltage - Supply:: 2.7V ~ 3.6V

Operating Temperature:: -40°C ~ 105°C (TA)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 24-TFBGA (6x8)

W25Q128JVBJQ FAQ

1.How can I place an order for W25Q128JVBJQ through Aetrix?

Please submit a Request for Quotation (RFQ) for W25Q128JVBJQ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for W25Q128JVBJQ reliable?

The price and inventory of W25Q128JVBJQ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for W25Q128JVBJQ is usually 5 days.

3.What payment methods are accepted for W25Q128JVBJQ?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for W25Q128JVBJQ transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for W25Q128JVBJQ?

W25Q128JVBJQ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your W25Q128JVBJQ order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for W25Q128JVBJQ?

For technical support, including W25Q128JVBJQ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your W25Q128JVBJQ requirements.

6.How does Aetrix verify that W25Q128JVBJQ is sourced from the original manufacturer or authorized distributors?

All W25Q128JVBJQ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that W25Q128JVBJQ meets industry standards.

7.What is the process for return or replacement of W25Q128JVBJQ?

All W25Q128JVBJQ units undergo pre-shipment inspection (PSI). If there is an issue with W25Q128JVBJQ, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The W25Q128JVBJQ part is unused and in its original packaging.

Return procedure for W25Q128JVBJQ:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…