Winbond Electronics Corporation W25Q128JVCIM TR
- Part No.:
- W25Q128JVCIM TR
- Manufacturer:
- Winbond Electronics Corporation
- Category:
- Memory
- Package:
- 24-TBGA
- Datasheet:
-
W25Q128JVCIM TR.pdf
- Description:
- IC FLASH 128MBIT SPI 24TFBGA
- Quantity:
- Payment:

- Shipping:

Inventory:4,820
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Product details
Overview
W25Q128JVCIM TR from Winbond is a 128M-bit (16MB) serial NOR flash memory IC supporting Dual/Quad SPI, QPI, and Double Transfer Rate (DTR) read modes. It operates from 2.7V to 3.6V, delivers up to 133MHz SPI clock speed (532MHz equivalent in Quad I/O), features uniform 4KB sectors, 100K program-erase cycles per sector, and 20-year data retention. It is used for code storage and XIP execution in microcontroller boot systems.
For engineers reviewing the W25Q128JVCIM TR datasheet, W25Q128JVCIM TR pinout, W25Q128JVCIM TR application, or W25Q128JVCIM TR equivalent, key selection criteria include DTR read support, /HOLD and /WP pin functionality in Standard/Dual SPI mode, Quad Enable (QE) bit configuration, 4KB sector granularity for firmware partitioning, and industrial temperature range (-40°C to +85°C).
Technical Context
The W25Q128JVCIM TR implements a flexible SPI-compatible command set with hardware and software reset capability, configurable /HOLD or /RESET pin behavior depending on QE status and package type, and volatile/non-volatile status register bits for fine-grained write protection. Its architecture supports erase suspend/resume, continuous read with wrap, and SFDP register for discoverable parameters.
It uses a 65,536-page array (256 bytes/page), organized into 4,096 erasable 4KB sectors and 256 erasable 64KB blocks. Quad SPI operation requires the non-volatile QE bit in Status Register-2 to be set, repurposing /WP and /HOLD as IO2 and IO3 - a configuration validated for this part number in SOIC-8 and WSON packages.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 128 M-bit (16 MB), enabling full MCU firmware image storage without external expansion |
| Interface Modes | Standard/Dual/Quad SPI, QPI, and DTR read - supports high-throughput XIP and fast boot loading |
| Max Clock Frequency | 133 MHz SPI; 266 MHz (Dual I/O), 532 MHz (Quad I/O) equivalent - exceeds parallel flash bandwidth in compact layout |
| Erase Granularity | Uniform 4 KB sectors, 32 KB and 64 KB blocks - allows precise firmware update partitioning and OTA safety |
| Endurance & Retention | 100,000 program-erase cycles per sector; >20 years data retention - suitable for field-upgradable embedded systems |
| Operating Voltage | 2.7 V to 3.6 V single supply - compatible with 3.3 V logic domains and low-power microcontrollers |
| Temperature Range | -40°C to +85°C (Industrial Grade) - validated for automotive body control and industrial HMI applications |
| Power-Down Current | 1 µA typical - enables ultra-low standby power in battery-backed or energy-harvesting systems |
Pinout & Package
W25Q128JVCIM TR is supplied in an 8-pin SOIC 208-mil (Package Code S) package. Pin functions are fully compatible with Winbond's W25Q128JV-DTR specification for this variant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| /CS | Chip Select Input | Active-low enable; high-impedance DO during deselect; required high-to-low transition before instruction acceptance |
| DO (IO1) | Data Output / I/O1 | Unidirectional output in Standard SPI; bidirectional I/O in Dual/Quad SPI; used for status/data reads on CLK falling edge |
| /WP (IO2) | Write Protect Input / I/O2 | Hardware lock for status register when QE=0; becomes IO2 in Quad SPI mode (QE=1) |
| GND | Ground Reference | Signal and power return path; must be low-impedance for stable timing and noise immunity |
| DI (IO0) | Data Input / I/O0 | Unidirectional input in Standard SPI; bidirectional I/O in Dual/Quad SPI; accepts instructions/addresses on CLK rising edge |
| CLK | Serial Clock Input | Master-generated timing signal; supports SPI Mode 0 and Mode 3; determines max throughput and setup/hold margins |
| /HOLD or /RESET (IO3) | Hold/Reset Input / I/O3 | Active-low pause during active /CS; configurable as /RESET only when QE=0 in 8-pin packages; disabled as /HOLD when QE=1 |
| VCC | Power Supply | 2.7–3.6 V supply; decoupling capacitor required near pin for transient current stability during page program/erase |
Key Features
| Feature | Design Value |
|---|---|
| DTR Read Support | Enables double-data-rate sampling on CLK edges, doubling effective throughput without increasing clock frequency |
| Continuous Read Mode | As few as 8 clocks overhead to address memory - minimizes instruction latency for XIP execution |
| Quad Peripheral Interface (QPI) | Reduces instruction overhead via 4-bit command/address/data bus - simplifies controller firmware and improves bandwidth efficiency |
| Security Registers | Three 256-byte OTP-lockable registers - support secure key storage, device authentication, and firmware integrity checks |
| Individual Sector Lock | Per-sector hardware/software lock via 32-bit security register or status register bits - prevents accidental overwrite of critical bootloader or calibration data |
| JEDEC ID & Unique Serial Number | 64-bit factory-programmed unique ID plus standard JEDEC manufacturer/device ID - enables automated BOM traceability and anti-counterfeiting |
Applications
| Bootloader Storage | Firmware Over-the-Air (OTA) |
|---|---|
Use Scenario: Storing primary bootloader and second-stage loader in embedded microcontrollers requiring cold-start reliability. IC Role / Device Role / Timing Role: Non-volatile code storage with XIP-capable Quad SPI interface; provides deterministic fetch latency during reset recovery. Use Value: 4KB sector erase enables atomic bootloader updates without risking corruption of active runtime code. | Use Scenario: Hosting field-upgradable application firmware in connected IoT gateways with limited PCB space. IC Role / Device Role / Timing Role: High-bandwidth firmware repository supporting DTR Fast Read Quad I/O (EDh) at 532 MHz equivalent rate. Use Value: 66 MB/s continuous transfer rate reduces OTA download time by >40% versus legacy SPI flash. |
| Industrial HMI Configuration | Automotive Body Control Module |
Use Scenario: Persisting UI theme assets, language packs, and calibration tables in factory-floor HMIs operating across wide temperature ranges. IC Role / Device Role / Timing Role: Parameter and asset storage with hardware write protection (/WP pin + BP bits) preventing unintended configuration loss. Use Value: -40°C to +85°C rating and 20-year data retention ensure UI consistency over product lifetime without refresh cycles. | Use Scenario: Storing diagnostic event logs, actuator calibration maps, and CAN message routing tables in 12V automotive ECUs. IC Role / Device Role / Timing Role: Reliable non-volatile data logger with erase suspend/resume capability for uninterrupted logging during ECU resets. Use Value: Erase/program suspend (75h/7Ah) allows log writes to continue after brief voltage dips common in vehicle power systems. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial NOR flash memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MX25L12833FZC-10G | 128M-bit, 104MHz max SPI clock, no DTR support, lacks QPI mode, 3.3V only, -40°C to +85°C | Suitable for cost-sensitive designs where DTR/QPI bandwidth is unnecessary and legacy SPI controllers dominate | Select when DTR read performance and QPI instruction reduction are not required; verify /HOLD and /WP pin compatibility in existing layout |
| S25FL128SAGMFI000 | 128M-bit, 133MHz SPI, supports DTR but no QPI, Cypress (Infineon) SFDP v1.6, 2.7–3.6V, -40°C to +105°C | Better suited for extended-temperature automotive applications requiring >85°C operation and AEC-Q100 alignment | Choose for under-hood modules needing +105°C rating; note absence of QPI may increase controller driver complexity |
Compared with W25Q128JVCIM TR, MX25L12833FZC-10G offers lower cost but sacrifices DTR and QPI bandwidth advantages, while S25FL128SAGMFI000 adds extended temperature support but omits QPI - making W25Q128JVCIM TR optimal for balanced industrial XIP and OTA throughput requirements.
Availability
W25Q128JVCIM TR is available at Aetrix Electronics and suitable for bootloader storage, firmware OTA updates, and industrial HMI configuration requiring stable component supply, long-term lifecycle assurance, and guaranteed industrial-grade temperature compliance.
Supply support for W25Q128JVCIM TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Winbond Electronics is a Taiwan-based semiconductor company specializing in specialty DRAM, mobile DRAM, and serial flash memory solutions for embedded and industrial markets.
The W25Q series targets high-performance, space-constrained applications requiring reliable code storage, XIP execution, and robust security - designed specifically for microcontroller boot, firmware update, and parameter retention use cases.
FAQ
What is the package type and pin count of the W25Q128JVCIM TR?
The W25Q128JVCIM TR uses an 8-pin SOIC 208-mil package (Package Code S). Its pinout includes /CS, DO (IO1), /WP (IO2), GND, DI (IO0), CLK, /HOLD or /RESET (IO3), and VCC - fully aligned with Winbond's W25Q128JV-DTR specification for industrial-grade variants.
Does the W25Q128JVCIM TR support Quad SPI and QPI modes?
Yes, the W25Q128JVCIM TR supports both Quad SPI and QPI modes. Quad SPI requires setting the non-volatile Quad Enable (QE) bit in Status Register-2; QPI mode is entered using instruction 38h and exited with FFh. Both modes use IO0–IO3 and deliver up to 532 MHz equivalent bandwidth.
Can the /HOLD and /WP pins be used simultaneously with Quad SPI enabled on the W25Q128JVCIM TR?
No. When QE = 1 (Quad SPI enabled), the /WP and /HOLD pins are reassigned as IO2 and IO3 respectively. Their hardware protection functions are disabled in Quad SPI mode. To retain /WP or /HOLD functionality, QE must be cleared (QE = 0), restricting operation to Standard or Dual SPI.
What is the endurance and data retention specification for the W25Q128JVCIM TR?
The W25Q128JVCIM TR guarantees a minimum of 100,000 program-erase cycles per 4KB sector and greater than 20 years of data retention at +85°C. These values are specified in the official Winbond W25Q128JV-DTR datasheet Revision C and apply directly to the W25Q128JVCIM TR industrial-grade variant.
Is the W25Q128JVCIM TR compatible with DTR (Double Transfer Rate) read operations?
Yes, the W25Q128JVCIM TR supports DTR read instructions including DTR Fast Read (0Dh), DTR Fast Read Dual I/O (BDh), and DTR Fast Read Quad I/O (EDh). These commands sample data on both clock edges, effectively doubling throughput without increasing clock frequency - a feature confirmed in the W25Q128JV-DTR datasheet.
W25Q128JVCIM TR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Winbond Electronics Corporation
- Series:
- SpiFlash®
- Package/Case:
- 24-TBGA
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH - NOR
- Memory Size:
- 128Mbit
- Memory Organization:
- 16M x 8
- Memory Interface:
- SPI - Quad I/O, QPI, DTR
- Clock Frequency:
- 133 MHz
- Write Cycle Time - Word, Page:
- 3ms
- Access Time:
- -
- Voltage - Supply:
- 2.7V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 24-TFBGA (6x8)
W25Q128JVCIM TR FAQ
1.How can I place an order for W25Q128JVCIM TR through Aetrix?
Please submit a Request for Quotation (RFQ) for W25Q128JVCIM TR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for W25Q128JVCIM TR reliable?
The price and inventory of W25Q128JVCIM TR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for W25Q128JVCIM TR is usually 5 days.
3.What payment methods are accepted for W25Q128JVCIM TR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for W25Q128JVCIM TR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for W25Q128JVCIM TR?
W25Q128JVCIM TR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your W25Q128JVCIM TR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for W25Q128JVCIM TR?
For technical support, including W25Q128JVCIM TR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your W25Q128JVCIM TR requirements.
6.How does Aetrix verify that W25Q128JVCIM TR is sourced from the original manufacturer or authorized distributors?
All W25Q128JVCIM TR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that W25Q128JVCIM TR meets industry standards.
7.What is the process for return or replacement of W25Q128JVCIM TR?
All W25Q128JVCIM TR units undergo pre-shipment inspection (PSI). If there is an issue with W25Q128JVCIM TR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The W25Q128JVCIM TR part is unused and in its original packaging.
Return procedure for W25Q128JVCIM TR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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