My Inquiry
My Account
Winbond Electronics Corporation W25Q128JVCIQ
- Part No.:
- W25Q128JVCIQ
- Manufacturer:
- Winbond Electronics Corporation
- Category:
- Memory
- Package:
- 24-TBGA
- Datasheet:
-
W25Q128JVCIQ.pdf
- Description:
- IC FLASH 128MBIT SPI 24TFBGA
- Quantity:
- Payment:
- Shipping:
Inventory:3,265
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
W25Q128JVCIQ from Winbond is a 128M-bit (16MB) serial NOR flash memory with Dual/Quad SPI interface, operating from 2.7V to 3.6V, supporting up to 133MHz clock frequency and 66MB/s continuous read throughput. It features uniform 4KB sectors, 100K program-erase cycles per sector, and 20+ year data retention - deployed in embedded boot code storage, firmware update partitions, and XIP-capable microcontroller systems.
For engineers reviewing the W25Q128JVCIQ datasheet, W25Q128JVCIQ pinout, W25Q128JVCIQ application, or W25Q128JVCIQ equivalent, key selection criteria include Quad SPI enable (QE bit), hardware /RESET availability in TFBGA/SOIC-16 packages, 4KB sector granularity for parameter storage, and JEDEC SFDP compliance for automatic configuration discovery.
Technical Context
The W25Q128JVCIQ implements a standard SPI bus (Mode 0/3) with optional Dual/Quad I/O extensions enabled via non-volatile QE bit in Status Register-2. Its command set includes Fast Read Quad I/O (EBh), enabling 532MHz effective throughput using IO0–IO3 bidirectional pins.
Internal architecture supports concurrent erase/program suspend/resume, individual sector lock via 3×256-byte security registers with OTP locks, and flexible protection schemes including top/bottom block protect (TB), complement array (CMP), and volatile/non-volatile BP bits - all managed through dedicated /WP and /HOLD pins or software commands.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 128 M-bit (16 MB), organized as 65,536 × 256-byte pages |
| Interface Support | Standard SPI + Dual SPI + Quad SPI; QE bit required for Quad mode |
| Max Clock Frequency | 133 MHz (single I/O); 266 MHz equiv. (Dual); 532 MHz equiv. (Quad) |
| Erase Granularity | 4 KB sector / 32 KB block / 64 KB block / full chip - enables fine-grained firmware partitioning |
| Endurance & Retention | 100,000 program-erase cycles per sector; >20 years data retention at +85°C |
| Operating Voltage | 2.7 V to 3.6 V - compatible with 3.3 V logic systems without level shifting |
| Temperature Range | −40°C to +85°C (Industrial Grade); −40°C to +105°C (Industrial Plus Grade) |
| Power Consumption | Typ. 1 µA in power-down mode; active read current <25 mA at 133 MHz |
Pinout & Package
W25Q128JVCIQ uses the 8-pin SOIC 208-mil package (Package Code S), with no dedicated /RESET pin - /HOLD functionality shares Pin 7. All I/O pins support Standard/Dual SPI; Quad SPI requires QE=1, repurposing /WP (Pin 3) as IO2 and /HOLD (Pin 7) as IO3.
| Pin | Circuit Role | Design Meaning |
|---|---|---|
| 1 /CS | Chip Select Input | Active-low enable; high-impedance DO during deselect; must transition H→L after power-up before first instruction |
| 2 DO (IO1) | Data Output / Quad I/O | Unidirectional output in Standard SPI; bidirectional IO1 in Dual/Quad modes; used for status/data reads |
| 3 /WP (IO2) | Write Protect Input / Quad I/O | Hardware write lock for status register; becomes IO2 when QE=1 - enables Quad SPI data lanes |
| 4 GND | Ground Reference | Primary return path for VCC and all I/O signals; critical for noise immunity in high-speed SPI |
| 5 DI (IO0) | Data Input / Quad I/O | Unidirectional input in Standard SPI; bidirectional IO0 in Dual/Quad modes; carries instructions/addresses |
| 6 CLK | Serial Clock Input | Edge-triggered timing reference; supports Mode 0 (CLK idle low) and Mode 3 (CLK idle high) |
| 7 /HOLD (IO3) | Hold Input / Quad I/O | Pauses ongoing SPI transfer; becomes IO3 when QE=1 - completes Quad I/O lane set (IO0–IO3) |
| 8 VCC | Power Supply | 2.7–3.6 V supply; decoupling capacitor required near pin for stable high-frequency operation |
Key Features
| Feature | Design Value |
|---|---|
| Quad SPI with Wrap-Around Read | Enables true XIP execution via 8/16/32/64-byte wrap modes - reduces address overhead and improves cache efficiency |
| JEDEC SFDP Register | Provides standardized, auto-discoverable configuration parameters (e.g., erase sizes, timing, voltage) - eliminates hard-coded driver assumptions |
| 64-bit Unique ID | Factory-programmed per-device serial number - supports secure firmware binding, device authentication, and field traceability |
| Erase/Program Suspend | Allows background erase or program to be paused for urgent read/write operations - essential for real-time system responsiveness |
| Three 256-byte Security Registers | OTP-lockable storage for keys, certificates, or calibration data - isolated from main array and protected by LB1–LB3 bits |
| Flexible Block Protection | Combines volatile/non-volatile BP bits, TB, SEC, and CMP to define arbitrary protected regions - supports multi-image boot and OTA update safety |
Applications
| Boot Code Storage | Firmware Update Partition |
|---|---|
|
Use Scenario: Storing primary bootloader and application firmware for ARM Cortex-M or RISC-V microcontrollers. IC Role / Device Role / Timing Role: Non-volatile code storage with XIP capability; delivers sequential instruction fetches at up to 66 MB/s via Quad SPI. Use Value: Eliminates external RAM copy step during boot; reduces BOM cost and boot latency by enabling direct execution from flash. |
Use Scenario: Isolating field-upgradable firmware images in dedicated memory regions with atomic erase boundaries. IC Role / Device Role / Timing Role: Parameter-aware storage partition; leverages 4KB sector erase to overwrite only changed image blocks. Use Value: Enables safe dual-bank OTA updates with rollback capability - no partial-write corruption risk due to uniform sector sizing. |
| Secure Configuration Storage | Industrial HMI Data Logging |
|
Use Scenario: Holding cryptographic keys, device certificates, and calibrated sensor offsets in tamper-resistant storage. IC Role / Device Role / Timing Role: Secure non-volatile register bank; uses OTP-locked security registers and individual sector lock commands. Use Value: Prevents unauthorized key extraction or configuration tampering - meets IEC 62443-3-3 SL2 requirements for embedded security. |
Use Scenario: Recording timestamped operational logs (e.g., temperature, pressure, fault codes) in factory automation controllers. IC Role / Device Role / Timing Role: High-endurance cyclic buffer; exploits 100K-cycle endurance and suspend/resume for uninterrupted logging during host interrupts. Use Value: Supports >10-year continuous logging at 100ms intervals without wear leveling controller - reduces firmware complexity. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial NOR flash applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MX25L12833FZC-10G | 128Mb, 104MHz max clock, no Quad Enable bit; uses legacy SPIMode only - no SFDP or unique ID | Lacks XIP optimization and auto-configuration; suitable for legacy SPI-only designs without security needs | Select when migrating from older Macronix platforms and Quad SPI is not required. |
| S25FL128SAGMFI000 | 128Mb, 133MHz, supports Octal DDR but requires different command set; includes on-die ECC and enhanced security engine | Higher reliability for automotive ECUs; adds ECC correction and secure debug disable - increases driver complexity | Choose for ASIL-B systems needing built-in ECC and certified security features beyond W25Q128JVCIQ scope. |
Compared with MX25L12833FZC-10G, W25Q128JVCIQ delivers faster Quad I/O throughput and standardized SFDP discovery; versus S25FL128SAGMFI000, it offers simpler integration and lower cost where ECC and automotive qualification are unnecessary.
Availability
W25Q128JVCIQ is available at Aetrix Electronics and suitable for industrial control firmware storage, medical device boot code hosting, and automotive infotainment subsystems requiring stable component supply across extended lifecycle programs.
Supply support for W25Q128JVCIQ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Winbond Electronics is a Taiwan-based semiconductor manufacturer specializing in specialty memory solutions, including NOR/NAND flash, SRAM, and mobile DRAM.
The W25Q series targets cost-sensitive, space-constrained embedded systems requiring high-speed serial code execution and robust firmware update capabilities - optimized for MCU-based IoT edge nodes and industrial HMIs.
FAQ
What is the package type and pin count of W25Q128JVCIQ?
W25Q128JVCIQ uses an 8-pin SOIC 208-mil package (Package Code S). It has no dedicated /RESET pin; Pin 7 serves as /HOLD in Standard/Dual SPI mode and becomes IO3 in Quad SPI mode when the QE bit is set. This matches the exact marking and mechanical specifications defined in Winbond's W25Q128JV datasheet Revision F.
Does W25Q128JVCIQ support Quad SPI operation out of the box?
No - W25Q128JVCIQ requires explicit configuration to enable Quad SPI. The non-volatile Quad Enable (QE) bit in Status Register-2 must be set to '1' via Write Status Register-2 (31h) instruction. Until then, Pins 3 (/WP) and 7 (/HOLD) remain dedicated hardware control lines, not I/O lanes. This behavior is confirmed in Section 4.2 and Figure 1a of the official datasheet.
How does W25Q128JVCIQ handle power-down and wake-up sequences?
W25Q128JVCIQ enters ultra-low-power mode (<1 µA typical) upon receiving Power-down (B9h) command. Wake-up occurs automatically when /CS transitions low, provided CLK remains stable. No separate release command is needed - the device resumes normal operation within tPUR (1 µs max) after /CS assertion. This sequence is specified in Section 8.2.21 and Table 9.3 of the datasheet.
Can W25Q128JVCIQ be used for secure key storage?
Yes - W25Q128JVCIQ includes three 256-byte Security Registers with One-Time-Programmable (OTP) lock bits (LB1–LB3). Once locked, these registers become read-only and are isolated from main array access. Keys written to them survive power cycles and resist software overwrite attempts - a feature documented in Sections 7.1.3 and 8.2.29–8.2.31 of the datasheet.
What is the minimum erase unit size supported by W25Q128JVCIQ?
W25Q128JVCIQ supports 4KB sector erase as its smallest erasable unit. The memory array contains 4,096 such sectors, enabling precise firmware patching and parameter updates without disturbing adjacent code or data. This granularity is fixed and cannot be subdivided - verified in Section 1 General Descriptions and Figure 2 of the datasheet.
W25Q128JVCIQ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Winbond Electronics Corporation
- Series:
- SpiFlash®
- Package/Case:
- 24-TBGA
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH - NOR
- Memory Size:
- 128Mbit
- Memory Organization:
- 16M x 8
- Memory Interface:
- SPI - Quad I/O, QPI
- Clock Frequency:
- 133 MHz
- Write Cycle Time - Word, Page:
- 3ms
- Access Time:
- -
- Voltage - Supply:
- 2.7V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 24-TFBGA (6x8)
W25Q128JVCIQ FAQ
1.How can I place an order for W25Q128JVCIQ through Aetrix?
Please submit a Request for Quotation (RFQ) for W25Q128JVCIQ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for W25Q128JVCIQ reliable?
The price and inventory of W25Q128JVCIQ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for W25Q128JVCIQ is usually 5 days.
3.What payment methods are accepted for W25Q128JVCIQ?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for W25Q128JVCIQ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for W25Q128JVCIQ?
W25Q128JVCIQ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your W25Q128JVCIQ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for W25Q128JVCIQ?
For technical support, including W25Q128JVCIQ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your W25Q128JVCIQ requirements.
6.How does Aetrix verify that W25Q128JVCIQ is sourced from the original manufacturer or authorized distributors?
All W25Q128JVCIQ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that W25Q128JVCIQ meets industry standards.
7.What is the process for return or replacement of W25Q128JVCIQ?
All W25Q128JVCIQ units undergo pre-shipment inspection (PSI). If there is an issue with W25Q128JVCIQ, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The W25Q128JVCIQ part is unused and in its original packaging.
Return procedure for W25Q128JVCIQ:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
W25Q128JVCIQ Tags
-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology
-
AT21CS01-STUM10-T
Microchip Technology
-
AT24C02C-SSHM-T
Microchip Technology
-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics
-
AT24CS02-SSHM-T
Microchip Technology
-
93LC46BT-I/OT
Microchip Technology
-
AT24C04C-SSHM-T
Microchip Technology
-
24LC01BT-I/SN
Microchip Technology
-
24AA02UIDT-I/OT
Microchip Technology
-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
