My Inquiry
My Account
Winbond Electronics Corporation W25Q128JVEJM
- Part No.:
- W25Q128JVEJM
- Manufacturer:
- Winbond Electronics Corporation
- Category:
- Memory
- Package:
- 8-WDFN Exposed Pad
- Datasheet:
-
W25Q128JVEJM.pdf
- Description:
- IC FLASH 128MBIT SPI/QUAD 8WSON
- Quantity:
- Payment:
- Shipping:
Inventory:2,331
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
W25Q128JVEJM from Winbond is a 128M-bit (16MB) serial NOR flash memory supporting Standard/Dual/Quad SPI, QPI, and DTR read modes. It operates from 2.7V to 3.6V, delivers up to 133MHz clock rate (532MHz equivalent Quad I/O), features uniform 4KB sectors, 100K program-erase cycles per sector, and 20+ year data retention. It serves as non-volatile code storage for microcontroller boot code, firmware updates, and parameter logging in space-constrained embedded systems.
For engineers reviewing the W25Q128JVEJM datasheet, W25Q128JVEJM pinout, W25Q128JVEJM application, or W25Q128JVEJM equivalent, key selection considerations include its 8-pin WSON 8x6-mm (Package Code E) footprint, /HOLD and /WP dual-function pins, Quad Enable (QE) bit dependency for IO2/IO3 mapping, and hardware reset availability only on SOIC-16 and TFBGA packages-not on WSON.
Technical Context
The W25Q128JVEJM implements a flexible SPI-compatible interface with mode-selectable operation: Standard SPI uses DI/DO unidirectionally; Dual/Quad SPI repurposes /WP and /HOLD as IO2/IO3 when QE=1 in Status Register-2; QPI enables 4-bit command/address/data transfers reducing instruction overhead. Its architecture includes a 256-byte page buffer, 4KB sector granularity, and three 256-byte security registers with OTP locks.
It supports erase suspend/resume, continuous read with wrap (8/16/32/64-byte), and JEDEC-compliant SFDP register for discoverable parameters. The device uses internal high-voltage generators for programming/erasing and includes volatile/non-volatile status bits for block protection (BP2–BP0), top/bottom selection (TB), and security lock (LB1–LB3).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 128 M-bit (16 MB), organized as 65,536 × 256-byte pages |
| Operating Voltage | 2.7 V to 3.6 V - compatible with standard 3.3 V logic rails and low-power MCU domains |
| Max Clock Frequency | 133 MHz SPI - enables 66 MB/s continuous read throughput in Quad I/O mode |
| Erase Granularity | Uniform 4 KB sectors (4,096 total), plus 32 KB and 64 KB blocks - supports fine-grained firmware partitioning |
| Endurance & Retention | 100,000 program-erase cycles per sector; >20 years data retention at +25°C - suitable for field-updatable systems |
| Interface Modes | Standard/Dual/Quad SPI, QPI, and DTR read - selectable via instruction set; QE bit controls IO2/IO3 mapping |
| Security Features | 64-bit unique ID, three 256-byte security registers with OTP locks, SFDP register - enables secure boot and device authentication |
Pinout & Package
W25Q128JVEJM is supplied in an 8-pad WSON 8×6-mm package (Package Code E), with exposed thermal pad. Pin functions are identical to the 8-pin SOIC 208-mil variant but in surface-mount form factor.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| /CS | Chip Select Input | Active-low enable; places DO/IO pins in high-impedance state when deasserted; required to transition high→low before new instruction acceptance |
| DO (IO1) | Data Output / Bidirectional I/O | Unidirectional output in Standard SPI; bidirectional I/O1 in Dual/Quad SPI/QPI; requires QE=1 for Quad use |
| /WP (IO2) | Write Protect Input / Bidirectional I/O | Hardware write-protection for status register when active low; becomes IO2 in Quad mode when QE=1 |
| GND | Ground Reference | Primary return path for VCC and all I/O signals; must be low-impedance for stable timing and noise immunity |
| DI (IO0) | Data Input / Bidirectional I/O | Unidirectional input in Standard SPI; bidirectional I/O0 in Dual/Quad SPI/QPI; always active in all modes |
| CLK | Serial Clock Input | Edge-triggered timing reference for all SPI/QPI operations; supports Mode 0 and Mode 3 clock polarity/idle states |
| /HOLD (IO3) | Hold Input / Bidirectional I/O | Pauses ongoing read/write while /CS is low; becomes IO3 in Quad mode when QE=1; not available as /RESET in WSON |
| VCC | Power Supply | Single 2.7–3.6 V supply; powers core logic, charge pumps, and I/O buffers; decoupling capacitor required near pin |
Key Features
| Feature | Design Value |
|---|---|
| Quad Peripheral Interface (QPI) | Reduces instruction overhead by encoding commands, addresses, and data in 4-bit nibbles - enables true XIP with minimal CPU intervention |
| Continuous Read Mode | As few as 8 clocks to address memory after instruction; supports wrap lengths of 8/16/32/64 bytes - optimizes burst reads for real-time firmware execution |
| Erase/Program Suspend & Resume | Allows background erase or program to be paused for higher-priority read access - essential for deterministic latency in RTOS-based systems |
| Flexible Hardware Write Protection | /WP pin + non-volatile BP/TB/SEC/CMP bits enable selective locking of 4KB sectors or entire array - prevents accidental firmware corruption during field updates |
| Discoverable Parameters (SFDP) | JEDEC-standard SFDP register provides programmable, versioned configuration data - eliminates hard-coded timing assumptions in bootloader design |
Applications
| Industrial PLC Firmware Storage | Automotive ADAS Boot Memory |
|---|---|
Use Scenario: Storing boot firmware and safety-critical configuration data in programmable logic controllers deployed in factory automation environments with wide temperature swings and EMI exposure. IC Role / Device Role / Timing Role: Non-volatile code storage with execute-in-place (XIP) capability via Quad SPI; provides deterministic read latency and immunity to power glitches during brown-out recovery. Use Value: 4KB sector granularity allows independent update of safety monitor routines without erasing full application image; 100K endurance ensures >10-year field life under frequent OTA update cycles. |
Use Scenario: Holding boot code and sensor calibration tables for radar/EPS ECUs operating in -40°C to +105°C automotive under-hood conditions. IC Role / Device Role / Timing Role: Primary boot memory accessed directly by ARM Cortex-R5/R7 cores; leverages QPI mode for sub-100ns instruction fetch latency and DTR read for high-throughput calibration data streaming. Use Value: 20+ year data retention and industrial-plus grade qualification guarantee integrity over vehicle lifetime; /WP pin + TB bit enable hardware-locked bootloader region immune to software faults. |
| IoT Edge Gateway Configuration | Medical Diagnostic Device Log Storage |
Use Scenario: Persisting network credentials, TLS certificates, and device-specific keys in cellular-connected gateways requiring FIPS-aligned secure storage. IC Role / Device Role / Timing Role: Secure parameter store using three OTP-lockable 256-byte security registers; 64-bit unique ID enables device identity binding in PKI workflows. Use Value: SFDP register allows runtime discovery of timing parameters - simplifies certification across multiple gateway SKUs with varying clock tree designs. |
Use Scenario: Recording time-stamped diagnostic waveforms and calibration logs in portable ultrasound and ECG devices where data integrity is regulated by IEC 62304. IC Role / Device Role / Timing Role: High-reliability data logger with sector-level wear leveling; erase suspend/resume permits uninterrupted waveform capture during background firmware validation. Use Value: Uniform 4KB sectors align with DICOM packet boundaries; 1µA typical power-down current extends battery life between clinical sessions without data loss. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial NOR flash applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MX25L12835FZC-10G | 128Mb density, 104MHz max clock, no DTR support, 3.3V-only, lacks SFDP register | Lower bandwidth; no DTR or QPI - unsuitable for XIP-critical designs requiring >50MB/s throughput | Select only if legacy SPI-only interface and cost sensitivity outweigh performance/security needs |
| S25FL128SAGMFI000 | 128Mb density, 133MHz clock, supports DTR and QPI, includes SFDP, but uses different security register layout and lacks OTP lock bits | Similar performance envelope but weaker cryptographic isolation - security registers writable without OTP enforcement | Prefer for Cypress ecosystem compatibility; avoid where regulatory compliance mandates hardware-enforced write protection |
Compared with MX25L12835FZC-10G and S25FL128SAGMFI000, the W25Q128JVEJM uniquely combines DTR read, QPI, SFDP, and OTP-locked security registers in a single 8-pad WSON package - making it optimal for next-generation secure, high-throughput embedded boot and logging applications.
Availability
W25Q128JVEJM is available at Aetrix Electronics and suitable for industrial control, automotive ADAS, IoT edge gateways, and medical diagnostics requiring stable component supply, long-term lifecycle assurance, and qualified industrial-plus grade operation.
Supply support for W25Q128JVEJM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Winbond Electronics is a Taiwan-based semiconductor company specializing in specialty DRAM, mobile DRAM, and serial flash memory solutions for embedded, communications, and consumer markets.
The W25Q series targets high-performance, secure, and space-constrained embedded systems - designed specifically to replace parallel NOR flash with superior density, lower pin count, and advanced interface flexibility including XIP-capable Quad SPI and QPI.
FAQ
What is the package type and footprint of W25Q128JVEJM?
W25Q128JVEJM uses an 8-pad WSON package measuring 8 mm × 6 mm (Package Code E) with an exposed thermal pad. It shares identical pinout and function mapping with the SOIC 208-mil variant but offers superior thermal performance and board-area efficiency for compact PCB layouts.
Does W25Q128JVEJM support hardware reset functionality?
No - W25Q128JVEJM does not include a dedicated /RESET pin. Hardware reset is only available on 16-pin SOIC and TFBGA packages. In the WSON 8-pin variant, the /HOLD pin (Pin 7) cannot be reconfigured as /RESET, even when QE=0, because the pinmux logic for reset is absent in this package option.
How is Quad SPI mode enabled on W25Q128JVEJM?
Quad SPI mode on W25Q128JVEJM is enabled by setting the Quad Enable (QE) bit in Status Register-2 (bit SR2[1]) to '1' via Write Status Register-2 (31h) instruction. Once set, /WP becomes IO2 and /HOLD becomes IO3 - both pins must be driven as bidirectional I/Os during Quad operations.
What is the purpose of the SFDP register in W25Q128JVEJM?
The SFDP (Serial Flash Discoverable Parameters) register in W25Q128JVEJM is a JEDEC-standard, read-only memory-mapped table that provides versioned, vendor-agnostic timing and functional parameters - enabling bootloader portability across flash vendors without hardcoded delay loops or configuration constants.
Can W25Q128JVEJM be used for execute-in-place (XIP) applications?
Yes - W25Q128JVEJM supports true XIP via Continuous Read Mode and Quad Peripheral Interface (QPI). With as few as 8 clocks to address memory and wrap lengths up to 64 bytes, it delivers deterministic, low-latency instruction fetches directly from flash to CPU, eliminating RAM copy overhead in resource-constrained MCUs.
W25Q128JVEJM Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Winbond Electronics Corporation
- Series:
- SpiFlash®
- Package/Case:
- 8-WDFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH - NOR
- Memory Size:
- 128Mbit
- Memory Organization:
- 16M x 8
- Memory Interface:
- SPI - Quad I/O, QPI, DTR
- Clock Frequency:
- 133 MHz
- Write Cycle Time - Word, Page:
- 3ms
- Access Time:
- -
- Voltage - Supply:
- 2.7V ~ 3.6V
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-WSON (8x6)
W25Q128JVEJM FAQ
1.How can I place an order for W25Q128JVEJM through Aetrix?
Please submit a Request for Quotation (RFQ) for W25Q128JVEJM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for W25Q128JVEJM reliable?
The price and inventory of W25Q128JVEJM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for W25Q128JVEJM is usually 5 days.
3.What payment methods are accepted for W25Q128JVEJM?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for W25Q128JVEJM transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for W25Q128JVEJM?
W25Q128JVEJM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your W25Q128JVEJM order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for W25Q128JVEJM?
For technical support, including W25Q128JVEJM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your W25Q128JVEJM requirements.
6.How does Aetrix verify that W25Q128JVEJM is sourced from the original manufacturer or authorized distributors?
All W25Q128JVEJM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that W25Q128JVEJM meets industry standards.
7.What is the process for return or replacement of W25Q128JVEJM?
All W25Q128JVEJM units undergo pre-shipment inspection (PSI). If there is an issue with W25Q128JVEJM, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The W25Q128JVEJM part is unused and in its original packaging.
Return procedure for W25Q128JVEJM:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
W25Q128JVEJM Tags
-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology
-
AT21CS01-STUM10-T
Microchip Technology
-
AT24C02C-SSHM-T
Microchip Technology
-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics
-
AT24CS02-SSHM-T
Microchip Technology
-
93LC46BT-I/OT
Microchip Technology
-
AT24C04C-SSHM-T
Microchip Technology
-
24LC01BT-I/SN
Microchip Technology
-
24AA02UIDT-I/OT
Microchip Technology
-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
