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Winbond Electronics Corporation W25Q128JVEJQ
- Part No.:
- W25Q128JVEJQ
- Manufacturer:
- Winbond Electronics Corporation
- Category:
- Memory
- Package:
- 8-WDFN Exposed Pad
- Datasheet:
-
W25Q128JVEJQ.pdf
- Description:
- IC FLASH 128MBIT SPI/QUAD 8WSON
- Quantity:
- Payment:
- Shipping:
Inventory:2,297
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Product details
Overview
W25Q128JVEJQ from Winbond is a 128M-bit (16MB) serial NOR flash memory IC supporting Standard, Dual, and Quad SPI interfaces with up to 133 MHz clock frequency, 4KB uniform sector architecture, and hardware write protection via /WP and /HOLD pins - deployed in embedded boot code storage, firmware update partitions, and XIP-capable microcontroller systems.
For engineers reviewing the W25Q128JVEJQ datasheet, W25Q128JVEJQ pinout, W25Q128JVEJQ application, or W25Q128JVEJQ equivalent, key selection criteria include Quad SPI enable (QE bit), 2.7–3.6V single-supply operation, 100K program-erase cycles per sector, -40°C to +105°C industrial-plus temperature grade, and compatibility with JEDEC SFDP and 64-bit unique ID for secure device identification.
Technical Context
The W25Q128JVEJQ implements a flexible SPI command set including Standard (DI/DO), Dual (IO0/IO1), and Quad (IO0–IO3) I/O modes, with non-volatile Quad Enable (QE) bit in Status Register-2 required to activate IO2 (/WP) and IO3 (/HOLD) for Quad operations. Its block diagram integrates a 256-byte page buffer, column/row decode logic, high-voltage generators, and three 256-byte security registers with OTP locks.
It supports erase granularity of 4KB sectors (4,096 total), 32KB blocks (2,048), and 64KB blocks (256), plus chip erase; features Erase/Program Suspend & Resume (75h/7Ah), continuous read with wrap (77h), and power-down mode consuming <1 µA typical. The /RESET pin is available only on SOIC-16 and TFBGA packages - not on the WSON 8x6-mm (E) package used by W25Q128JVEJQ.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 128 M-bit (16 MB), organized as 65,536 × 256-byte programmable pages |
| SPI Interface Modes | Standard (DI/DO), Dual (IO0/IO1), Quad (IO0–IO3); QE bit must be set for Quad I/O |
| Max Clock Frequency | 133 MHz (single I/O); 266 MHz equiv. (Dual I/O); 532 MHz equiv. (Quad I/O) |
| Erase Granularity | 4 KB sector (4,096 sectors), 32 KB block (2,048 blocks), 64 KB block (256 blocks), full chip |
| Endurance & Retention | 100,000 program-erase cycles per sector; >20 years data retention at +25°C |
| Operating Voltage | 2.7 V to 3.6 V single supply; no external voltage regulators required |
| Temperature Range | -40°C to +105°C (Industrial Plus grade), qualified per AEC-Q100 Class 2 for automotive-adjacent use |
| Power Consumption | <1 µA typical in power-down mode (B9h); active read current ~25 mA at 133 MHz |
Pinout & Package
W25Q128JVEJQ uses the 8-pad WSON 8x6-mm package (Package Code E), with exposed thermal pad. Pin functions are identical to the 8-pin SOIC 208-mil variant but in a smaller, surface-mount footprint optimized for space-constrained PCB layouts.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 /CS | Chip Select Input | Active-low enable; high-impedance DO/IO outputs when deasserted; must transition high→low after power-up before first instruction |
| 2 DO (IO1) | Data Output / Bidirectional I/O | Unidirectional output in Standard SPI; bidirectional I/O in Dual/Quad modes; used for status/data reads on falling CLK edge |
| 3 /WP (IO2) | Write Protect Input / Bidirectional I/O | Hardware write-protection enable (active low); becomes IO2 in Quad mode when QE=1; requires external pull-up if unused |
| 4 GND | Ground Reference | Primary signal and power return path; must be low-inductance connection to minimize noise during high-speed reads |
| 5 DI (IO0) | Data Input / Bidirectional I/O | Unidirectional input in Standard SPI; bidirectional I/O in Dual/Quad modes; accepts instructions/addresses/data on rising CLK edge |
| 6 CLK | Serial Clock Input | Master-generated timing reference; supports SPI Mode 0 (CPOL=0, CPHA=0) and Mode 3 (CPOL=1, CPHA=1) |
| 7 /HOLD (IO3) | Hold Input / Bidirectional I/O | Pauses ongoing SPI transaction when asserted low; becomes IO3 in Quad mode when QE=1; not functional during Quad operation unless disabled |
| 8 VCC | Power Supply | 2.7–3.6 V supply; decoupling capacitor (≥1 µF ceramic) required within 5 mm of pin for stable high-frequency operation |
Key Features
| Feature | Design Value |
|---|---|
| Quad SPI with 532 MHz equiv. bandwidth | Enables XIP execution and fast firmware loading without external parallel bus; reduces MCU pin count and PCB routing complexity |
| Uniform 4KB sector erase | Allows fine-grained firmware partitioning (e.g., bootloader vs. application vs. config), minimizing wear on critical regions |
| Volatile & non-volatile status register bits | Supports field-upgradable protection schemes (BP0–BP2, TB, SEC, CMP) with both immediate and power-cycle persistent settings |
| Three 256-byte security registers | Provide dedicated, OTP-lockable storage for keys, calibration data, or device-specific credentials - isolated from main array |
| JEDEC SFDP and 64-bit unique ID | Enables automatic driver configuration and unambiguous device identity in multi-flash systems or secure provisioning workflows |
| Erase/program suspend & resume | Permits time-critical foreground tasks (e.g., sensor sampling) to interrupt background flash operations without data loss or timeout risk |
Applications
| Boot Code Storage | Firmware Update Partition |
|---|---|
|
Use Scenario: Storing primary bootloader and initial firmware image for ARM Cortex-M or RISC-V MCUs requiring cold-start execution. IC Role / Device Role / Timing Role: Non-volatile code storage with XIP support via Quad SPI; delivers deterministic 66 MB/s sequential read throughput. Use Value: Eliminates need for external RAM copy during boot; reduces BOM cost and boot latency by >40% vs. parallel NOR flash. |
Use Scenario: Dedicated, isolated memory region for over-the-air (OTA) firmware updates in industrial gateways and connected sensors. IC Role / Device Role / Timing Role: Secure, wear-leveling-aware update staging area with individual sector lock/unlock (36h/39h) and suspend/resume (75h/7Ah). Use Value: Enables atomic firmware swaps with rollback capability; prevents partial writes during power loss using status register protection (SRP/SRL). |
| Secure Configuration Storage | Audio/Log Data Buffer |
|
Use Scenario: Storing calibrated sensor offsets, cryptographic keys, and device-specific identifiers in medical or automotive control units. IC Role / Device Role / Timing Role: Tamper-resistant storage using three OTP-lockable 256-byte security registers and hardware write-protect (/WP) with CMP/TB bits. Use Value: Meets ISO 26262 ASIL-B requirements for integrity-critical parameters; prevents unauthorized modification without physical access or OTP unlock sequence. |
Use Scenario: Circular buffer for audio samples or diagnostic logs in voice-enabled IoT endpoints and predictive maintenance sensors. IC Role / Device Role / Timing Role: High-endurance 4KB sector storage with 100K erase cycles; supports rapid 256-byte page programming and fast 4KB sector erase. Use Value: Sustains >10 years of daily logging at 100 writes/sec; outperforms EEPROM in density and speed while avoiding wear leveling firmware overhead. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial NOR flash applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MX25L12833FZC-10G | 128 M-bit, 104 MHz max clock, SOIC-8 only; lacks Quad I/O and security registers | No XIP support beyond 66 MHz; no SFDP or unique ID; limited to basic code storage | Choose for cost-sensitive, non-XIP designs where Quad SPI and security are unnecessary |
| S25FL128SAGMFI000 | 128 M-bit, 133 MHz, Quad SPI, SFDP, and 64-bit ID; includes on-die ECC and configurable dummy cycles | Better read reliability in noisy environments; supports configurable latency for mixed-speed systems | Prefer when system-level ECC or adaptive timing is required; higher unit cost than W25Q128JVEJQ |
Compared with MX25L12833FZC-10G, W25Q128JVEJQ enables faster XIP and secure provisioning; versus S25FL128SAGMFI000, it trades on-die ECC for lower latency and broader vendor toolchain support, making it optimal for real-time boot and OTA update pipelines.
Availability
W25Q128JVEJQ is available at Aetrix Electronics and suitable for industrial control panels, automotive telematics modules, and medical imaging subsystems requiring stable component supply across extended product lifecycles.
Supply support for W25Q128JVEJQ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Winbond Electronics is a Taiwan-based semiconductor manufacturer specializing in specialty DRAM, mobile DRAM, and serial flash memory solutions since 1987.
The W25Q series targets high-reliability embedded systems needing scalable, SPI-compatible non-volatile storage with industrial temperature support, security extensions, and XIP readiness - directly addressing boot, firmware, and configuration needs in resource-constrained designs.
FAQ
What is the package type and footprint of W25Q128JVEJQ?
W25Q128JVEJQ uses the 8-pad WSON 8x6-mm package (Package Code E), with an exposed thermal pad. It shares identical pinout and function mapping with the SOIC-208 variant but offers 40% smaller board area and improved thermal performance for high-density layouts. The footprint complies with JEDEC MO-241AC standards and requires solder paste stencil design per IPC-7351B.
Does W25Q128JVEJQ support hardware reset (/RESET) functionality?
No - W25Q128JVEJQ does not include a dedicated /RESET pin. The /RESET function is only available on SOIC-16 (Package Code F) and TFBGA (Package Codes B/C) variants. On W25Q128JVEJQ, reset must be performed via software sequence: Enable Reset (66h) followed by Reset Device (99h), which takes ~30 µs. This is fully supported and deterministic for all operational states.
How is Quad SPI enabled on W25Q128JVEJQ?
Quad SPI is enabled by setting the Quad Enable (QE) bit in Status Register-2 (bit 1). This is done via Write Status Register-2 (31h) instruction. Once QE=1, the /WP and /HOLD pins become IO2 and IO3 respectively, enabling four-line data transfer. The change persists across power cycles unless explicitly cleared, and QE status can be verified using Read Status Register-2 (35h).
What security features does W25Q128JVEJQ provide beyond standard write protection?
W25Q128JVEJQ provides layered security: (1) Three 256-byte OTP-lockable security registers for keys or credentials; (2) Individual sector/block lock/unlock (36h/39h); (3) Complement protect (CMP) and top/bottom array protection (TB); (4) Status register lock (SRP/SRL) preventing accidental configuration changes; and (5) 64-bit unique ID for device authentication - all accessible via standard SPI commands without additional controllers.
Can W25Q128JVEJQ operate in SPI Mode 3 (CPOL=1, CPHA=1)?
Yes - W25Q128JVEJQ supports both SPI Mode 0 (CPOL=0, CPHA=0) and Mode 3 (CPOL=1, CPHA=1). In Mode 3, the CLK signal idles high between transactions, and data is sampled on the falling edge and shifted on the rising edge. This compatibility allows seamless integration with legacy or specialized MCU SPI peripherals that mandate Mode 3 timing.
W25Q128JVEJQ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Winbond Electronics Corporation
- Series:
- SpiFlash®
- Package/Case:
- 8-WDFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH - NOR
- Memory Size:
- 128Mbit
- Memory Organization:
- 16M x 8
- Memory Interface:
- SPI - Quad I/O, QPI, DTR
- Clock Frequency:
- 133 MHz
- Write Cycle Time - Word, Page:
- 3ms
- Access Time:
- -
- Voltage - Supply:
- 2.7V ~ 3.6V
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-WSON (8x6)
W25Q128JVEJQ FAQ
1.How can I place an order for W25Q128JVEJQ through Aetrix?
Please submit a Request for Quotation (RFQ) for W25Q128JVEJQ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for W25Q128JVEJQ reliable?
The price and inventory of W25Q128JVEJQ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for W25Q128JVEJQ is usually 5 days.
3.What payment methods are accepted for W25Q128JVEJQ?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for W25Q128JVEJQ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for W25Q128JVEJQ?
W25Q128JVEJQ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your W25Q128JVEJQ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for W25Q128JVEJQ?
For technical support, including W25Q128JVEJQ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your W25Q128JVEJQ requirements.
6.How does Aetrix verify that W25Q128JVEJQ is sourced from the original manufacturer or authorized distributors?
All W25Q128JVEJQ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that W25Q128JVEJQ meets industry standards.
7.What is the process for return or replacement of W25Q128JVEJQ?
All W25Q128JVEJQ units undergo pre-shipment inspection (PSI). If there is an issue with W25Q128JVEJQ, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The W25Q128JVEJQ part is unused and in its original packaging.
Return procedure for W25Q128JVEJQ:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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