Winbond Electronics Corporation W25Q128JVEJQ TR
- Part No.:
- W25Q128JVEJQ TR
- Manufacturer:
- Winbond Electronics Corporation
- Category:
- Memory
- Package:
- 8-WDFN Exposed Pad
- Datasheet:
-
W25Q128JVEJQ TR.pdf
- Description:
- IC FLASH 128MBIT SPI/QUAD 8WSON
- Quantity:
- Payment:

- Shipping:

Inventory:1,505
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Product details
Overview
W25Q128JVEJQ TR from Winbond is a 128M-bit (16MB) serial NOR flash memory IC supporting Standard, Dual, and Quad SPI interfaces for embedded code storage and XIP execution. It operates from 2.7V to 3.6V, delivers up to 133MHz SPI clock rate (532MHz equivalent in Quad I/O), and features 4KB uniform sectors, 100K program-erase cycles, and -40°C to +105°C industrial-plus temperature grade.
For engineers reviewing the W25Q128JVEJQ TR datasheet, W25Q128JVEJQ TR pinout, W25Q128JVEJQ TR application, or W25Q128JVEJQ TR equivalent, key selection considerations include Quad SPI enable (QE bit), /HOLD vs /RESET pin availability per package, 4KB sector granularity for firmware partitioning, and hardware write protection via /WP and status register bits.
Technical Context
The W25Q128JVEJQ TR implements a SPI-compatible command set with three operational modes: Standard (DI/DO), Dual (IO0/IO1), and Quad (IO0–IO3), where Quad mode requires non-volatile QE bit (SR2[1]) set. Its architecture includes a 256-byte page buffer, 4,096 erasable 4KB sectors, and dedicated security registers with OTP locks.
It supports JEDEC-standard device ID (9Fh), SFDP (5Ah), and 64-bit unique serial number (4Bh). Erase/program suspend/resume (75h/7Ah), continuous read with wrap (77h), and power-down (B9h) with 1µA typical standby current enable low-power embedded boot and data logging use cases.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 128 M-bit (16 MB), organized as 65,536 × 256-byte pages |
| SPI Interface Modes | Standard (DI/DO), Dual (IO0/IO1), Quad (IO0–IO3); QE bit required for Quad I/O |
| Max Clock Frequency | 133 MHz single-ended; enables 532 MB/s effective throughput in Quad I/O Fast Read |
| Erase Granularity | Uniform 4KB sectors, 32KB blocks, 64KB blocks, and full-chip erase - supports fine-grained firmware updates |
| Endurance & Retention | 100,000 program/erase cycles per sector; >20-year data retention at +85°C |
| Operating Voltage | 2.7 V to 3.6 V - compatible with 3.3V logic systems without level shifting |
| Temperature Grade | Industrial Plus: –40°C to +105°C - qualified for extended-temperature automotive and industrial control |
| Power-Down Current | 1 µA typical - enables ultra-low-power sleep states in battery-backed or energy-harvested devices |
Pinout & Package
W25Q128JVEJQ TR uses the 8-pad WSON 8x6-mm package (Package Code E), with exposed thermal pad. Pin functions are identical to SOIC-208 and WSON-6x5 variants, but excludes dedicated /RESET - /HOLD (IO3) shares pin 7.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 /CS | Chip Select Input | Active-low enable; high-impedance DO during deselect; must transition high→low after power-up to accept commands |
| 2 DO (IO1) | Data Output / Bidirectional I/O | Unidirectional output in Standard SPI; bidirectional IO1 in Dual/Quad modes; used for status/data reads |
| 3 /WP (IO2) | Write Protect Input / Bidirectional I/O | Hardware lock for status register when low; becomes IO2 in Quad mode if QE=1 |
| 4 GND | Ground Reference | Primary return path for VCC and all I/O signals; connects to thermal pad for thermal dissipation |
| 5 DI (IO0) | Data Input / Bidirectional I/O | Unidirectional input in Standard SPI; bidirectional IO0 in Dual/Quad modes; carries instructions, addresses, data |
| 6 CLK | Serial Clock Input | Edge-triggered timing reference; supports SPI Mode 0 and Mode 3; max 133 MHz frequency |
| 7 /HOLD (IO3) | Hold Input / Bidirectional I/O | Pauses ongoing transfers when low (active-low); becomes IO3 in Quad mode if QE=1; no /RESET function in this package |
| 8 VCC | Power Supply | 2.7–3.6 V supply; decoupling capacitor required near pin for stable operation during fast read/write bursts |
Key Features
| Feature | Design Value |
|---|---|
| Quad SPI with QE bit control | Enables 4-line data transfer (IO0–IO3) only when Status Register-2 bit QE=1 - prevents accidental mode change |
| 4KB uniform sector architecture | Allows independent firmware image, parameter, and log storage partitions - critical for OTA update safety and wear leveling |
| Erase/Program Suspend & Resume | Permits background interrupt handling (e.g., real-time sensor sampling) while flash operations execute - reduces system latency |
| Three 256-byte Security Registers | OTP-lockable storage for keys, calibration data, or secure boot manifests - isolated from main array and protected by LB1–LB3 bits |
| Hardware Write Protection (/WP) | Physically blocks status register writes when asserted - complements software BP bits for tamper-resistant configuration lockdown |
| 64-bit Unique Serial Number | Factory-programmed per-device identifier - enables secure device authentication and traceability in production and field deployment |
Applications
| Industrial PLC Firmware Storage | Automotive ADAS Boot Memory |
|---|---|
|
Use Scenario: Storing firmware images and configuration tables for programmable logic controllers operating in harsh factory environments. IC Role / Device Role / Timing Role: Primary non-volatile code storage with XIP support; provides deterministic boot timing via Fast Read Quad I/O. Use Value: 4KB sector erase enables incremental firmware patching without full reflash; -40°C to +105°C rating ensures reliability in uncontrolled cabinet temperatures. |
Use Scenario: Hosting boot code and safety-critical microcode for radar/EPS ECUs requiring ASIL-B compliance and rapid startup. IC Role / Device Role / Timing Role: Secure boot memory with SFDP-defined timing parameters and 64-bit UID for cryptographic binding. Use Value: 100K endurance and 20-year retention guarantee long service life; hardware /WP + status register protection prevents runtime corruption. |
| Medical IoT Sensor Node Data Log | Smart Energy Meter Firmware & Calibration |
|
Use Scenario: Capturing timestamped physiological readings in portable diagnostic devices with intermittent power. IC Role / Device Role / Timing Role: Dual-purpose storage: executable firmware + circular data buffer using sector-level wear leveling. Use Value: 1µA power-down current extends battery life; erase suspend allows concurrent sensor acquisition and flash logging. |
Use Scenario: Storing metrology firmware, tariff tables, and factory calibration constants in utility-grade electricity meters. IC Role / Device Role / Timing Role: Tamper-resistant configuration storage with OTP-locked security registers for calibration integrity. Use Value: Individual sector lock (36h/39h) isolates calibration data from firmware updates; JEDEC ID and SFDP ensure supply chain authenticity. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial NOR flash memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MX25L12833FZC-10G | 128Mb, 104MHz max clock, SOIC-8 only; no Quad I/O support; lacks security registers and UID | Lower-cost option for basic code storage without XIP or security requirements | Select when Quad SPI bandwidth and cryptographic features are unnecessary; verify /HOLD compatibility in legacy designs |
| S25FL128SAGMFI000 | 128Mb, 133MHz, supports Octal DTR; includes on-die ECC and configurable reset polarity; TFBGA-only | Targeted at high-reliability aerospace/industrial systems needing error correction and flexible reset signaling | Choose when ECC, Octal interface, or hardware reset (/RESET pin) is mandatory; not drop-in due to package and pinout differences |
Compared with W25Q128JVEJQ TR, MX25L12833FZC-10G offers cost savings but sacrifices Quad I/O speed and security features, while S25FL128SAGMFI000 adds ECC and Octal capability at the expense of broader package availability and higher BOM cost.
Availability
W25Q128JVEJQ TR is available at Aetrix Electronics and suitable for industrial automation, automotive electronics, and medical IoT applications requiring stable component supply, long-term lifecycle assurance, and industrial-plus temperature qualification.
Supply support for W25Q128JVEJQ TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Winbond Electronics is a Taiwan-based semiconductor manufacturer specializing in specialty memory solutions, including SPI NOR/NAND flash, RAM, and mobile DRAM.
The W25Q series targets embedded systems requiring high-speed, secure, and reliable serial flash for code execution and data storage - optimized for industrial, automotive, and networking applications.
FAQ
What is the package type and footprint of W25Q128JVEJQ TR?
W25Q128JVEJQ TR uses an 8-pin WSON package measuring 8 mm × 6 mm (Package Code E) with an exposed thermal pad. It shares pinout and electrical characteristics with the WSON-6x5 variant but offers improved thermal performance due to larger body size. The footprint matches standard WSON-8 land patterns with 0.5 mm pitch.
Does W25Q128JVEJQ TR support hardware reset (/RESET pin)?
No, W25Q128JVEJQ TR does not include a dedicated /RESET pin. That function is only available on SOIC-16 (Package Code F) and TFBGA (Package Codes B/C) variants. In W25Q128JVEJQ TR, pin 7 serves as /HOLD (or IO3 in Quad mode), and system-level reset must be implemented via software sequence (66h + 99h) or external power-cycle control.
How is Quad SPI mode enabled on W25Q128JVEJQ TR?
Quad SPI mode on W25Q128JVEJQ TR is enabled by setting the Quad Enable (QE) bit - bit 1 of Status Register-2 - to '1' using instruction 31h. This is a non-volatile write; once set, IO2 (/WP) and IO3 (/HOLD) become active bidirectional data lines. The device must be in Standard or Dual mode before issuing the write, and /WP must be deasserted during the operation.
What is the purpose of the /WP pin on W25Q128JVEJQ TR?
The /WP pin on W25Q128JVEJQ TR provides hardware-level write protection for the status register when held low. It works in conjunction with status register bits (SRP, BP2–BP0, TB, SEC) to prevent accidental or malicious modification of memory protection settings. When QE=1, /WP becomes IO2 and loses its hardware protect function.
Can W25Q128JVEJQ TR be used for Execute-in-Place (XIP) applications?
Yes, W25Q128JVEJQ TR supports true XIP operation via Fast Read Quad I/O (EBh) and continuous read with wrap (77h), enabling direct code execution from flash without copying to RAM. Its 133MHz clock and 532MB/s effective throughput meet real-time latency requirements for MCU boot and firmware overlay in resource-constrained systems.
W25Q128JVEJQ TR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Winbond Electronics Corporation
- Series:
- SpiFlash®
- Package/Case:
- 8-WDFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH - NOR
- Memory Size:
- 128Mbit
- Memory Organization:
- 16M x 8
- Memory Interface:
- SPI - Quad I/O, QPI, DTR
- Clock Frequency:
- 133 MHz
- Write Cycle Time - Word, Page:
- 3ms
- Access Time:
- -
- Voltage - Supply:
- 2.7V ~ 3.6V
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-WSON (8x6)
W25Q128JVEJQ TR FAQ
1.How can I place an order for W25Q128JVEJQ TR through Aetrix?
Please submit a Request for Quotation (RFQ) for W25Q128JVEJQ TR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for W25Q128JVEJQ TR reliable?
The price and inventory of W25Q128JVEJQ TR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for W25Q128JVEJQ TR is usually 5 days.
3.What payment methods are accepted for W25Q128JVEJQ TR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for W25Q128JVEJQ TR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for W25Q128JVEJQ TR?
W25Q128JVEJQ TR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your W25Q128JVEJQ TR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for W25Q128JVEJQ TR?
For technical support, including W25Q128JVEJQ TR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your W25Q128JVEJQ TR requirements.
6.How does Aetrix verify that W25Q128JVEJQ TR is sourced from the original manufacturer or authorized distributors?
All W25Q128JVEJQ TR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that W25Q128JVEJQ TR meets industry standards.
7.What is the process for return or replacement of W25Q128JVEJQ TR?
All W25Q128JVEJQ TR units undergo pre-shipment inspection (PSI). If there is an issue with W25Q128JVEJQ TR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The W25Q128JVEJQ TR part is unused and in its original packaging.
Return procedure for W25Q128JVEJQ TR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
W25Q128JVEJQ TR Tags

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M24C02-WMN6TP
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AT24C04C-SSHM-T
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