Winbond Electronics Corporation W25Q128JVFJM TR
- Part No.:
- W25Q128JVFJM TR
- Manufacturer:
- Winbond Electronics Corporation
- Category:
- Memory
- Package:
- 16-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
W25Q128JVFJM TR.pdf
- Description:
- IC FLASH 128MBIT SPI/QUAD 16SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:4,758
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Product details
Overview
W25Q128JVFJM TR from Winbond is a 128M-bit (16MB) serial NOR flash memory supporting Standard/Dual/Quad SPI, QPI, and DTR read modes. It operates from 2.7V to 3.6V, delivers up to 133MHz clock rate (532MHz equivalent Quad I/O), features uniform 4KB sectors, 100K program-erase cycles per sector, and 20-year data retention. It serves as nonvolatile code storage and XIP execution memory in microcontroller boot systems.
For engineers reviewing the W25Q128JVFJM TR datasheet, W25Q128JVFJM TR pinout, W25Q128JVFJM TR application, or W25Q128JVFJM TR equivalent, key selection criteria include Quad Enable (QE) bit configuration, /HOLD vs /RESET pin availability per package, DTR timing compliance, and sector protection granularity for firmware update safety.
Technical Context
The W25Q128JVFJM TR implements a flexible SPI-compatible command set with volatile/non-volatile status register control (BP2–BP0, TB, SEC, QE, DRV0/DRV1, HOLD/RST). Its architecture supports true execute-in-place (XIP) via Continuous Read Mode with ≤8-clock instruction overhead and wrap lengths of 8/16/32/64 bytes.
It integrates three 256-byte security registers with OTP locks, JEDEC-standard 64-bit unique ID, SFDP register for discoverable parameters, and hardware write protection using /WP and /HOLD pins - both repurposed as IO2/IO3 when QE=1 in Quad mode. Erase suspend/resume and power-down (<1µA typical) enable low-power embedded operation.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 128 M-bit (16 MB), organized as 65,536 × 256-byte pages |
| Operating Voltage | 2.7 V to 3.6 V - compatible with standard 3.3 V logic rails and industrial supply tolerances |
| Max Clock Frequency | 133 MHz (SPI/QPI); enables 66 MB/s continuous read throughput in Quad I/O mode |
| Erase Granularity | Uniform 4 KB sectors (4,096 total), plus 32 KB and 64 KB blocks - supports fine-grained firmware partitioning |
| Endurance & Retention | 100,000 program-erase cycles per sector; >20 years data retention at +85°C |
| Interface Modes | Standard SPI, Dual SPI, Quad SPI, QPI, and DTR-capable read instructions - selectable via status register and command set |
| Temperature Range | –40°C to +105°C - qualified for industrial-plus grade applications including automotive infotainment and motor control |
Pinout & Package
W25Q128JVFJM TR uses an 8-pin WSON 6×5-mm package (Package Code P), with exposed pad for thermal dissipation. Pin functions are defined per JEDEC-standard SOIC/WSON layout and validated for this exact variant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| /CS | Chip Select Input | Active-low enable; places DO/IO pins in high-impedance state when deasserted; required to transition high→low before new instruction acceptance |
| DO (IO1) | Data Output / I/O1 | Unidirectional output in Standard SPI; bidirectional I/O in Dual/Quad modes; used for status/data reads on CLK falling edge |
| /WP (IO2) | Write Protect Input / I/O2 | Hardware lock for status register writes; disabled as IO2 when Quad Enable (QE) bit = 1 |
| GND | Ground Reference | Primary signal and power return path; must be low-impedance for stable read/write timing and noise immunity |
| DI (IO0) | Data Input / I/O0 | Unidirectional input in Standard SPI; bidirectional I/O in Dual/Quad modes; accepts instructions/addresses on CLK rising edge |
| CLK | Serial Clock Input | Master-generated timing reference; supports SPI Mode 0 and Mode 3; determines max interface speed and setup/hold margins |
| /HOLD (IO3) | Hold Input / I/O3 | Pauses ongoing read/write without deselecting device; disabled as IO3 when QE = 1 |
| VCC | Power Supply | Single 2.7–3.6 V supply; powers internal charge pumps, logic, and I/O buffers; requires local 100 nF decoupling |
Key Features
| Feature | Design Value |
|---|---|
| Quad Peripheral Interface (QPI) | Reduces instruction overhead by encoding commands in 4-bit nibbles - enables faster sequential access than standard SPI |
| DTR (Double Transfer Rate) Read | Transfers data on both clock edges during read operations - doubles effective bandwidth without increasing clock frequency |
| Continuous Read with Wrap | Supports 8/16/32/64-byte burst wraps - eliminates address increment overhead for streaming code or audio buffers |
| Individual Sector Lock | Allows per-sector (4 KB) write protection via 32-bit lock bits - isolates bootloader, calibration data, and user settings |
| Security Registers (3 × 256 B) | OTP-lockable nonvolatile storage for keys, certificates, or device-specific secrets - separate from main array and protected by LB1–LB3 bits |
Applications
| Bootloader Storage | Firmware Over-the-Air (OTA) |
|---|---|
Use Scenario: Storing primary bootloader and secondary stage firmware in embedded microcontrollers with no external parallel bus. IC Role / Device Role / Timing Role: Nonvolatile code storage with XIP capability; executes directly from flash via Quad SPI with <8-clock address overhead. Use Value: Eliminates RAM copy latency and reduces BOM cost versus parallel NOR; supports secure boot via locked bootloader sector. | Use Scenario: Receiving and validating encrypted firmware updates in connected IoT gateways operating in field-deployed environments. IC Role / Device Role / Timing Role: Dual-bank update storage - one bank active, one bank receiving new image; uses sector erase and page program with suspend/resume. Use Value: Enables atomic firmware swaps with zero downtime; 4KB sector granularity allows differential patching and rollback support. |
| Industrial HMI Display Memory | Automotive Infotainment UI Assets |
Use Scenario: Holding GUI assets (fonts, icons, bitmaps) and localized language strings for programmable HMIs in PLCs and CNC controllers. IC Role / Device Role / Timing Role: High-bandwidth serial memory accessed via QPI mode; supplies pixel data streams to display controller DMA engines. Use Value: 66 MB/s read throughput meets 800×480@60Hz RGB565 refresh requirements; -40°C to +105°C rating ensures reliability in factory-floor enclosures. | Use Scenario: Storing UI skins, voice prompt audio, and navigation map tiles in automotive head units requiring AEC-Q100 alignment. IC Role / Device Role / Timing Role: Industrial-plus grade serial flash with unique 64-bit ID and security registers - used for anti-cloning and content licensing enforcement. Use Value: Security registers store decryption keys for encrypted UI assets; OTP lock prevents runtime key extraction during service diagnostics. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial NOR flash memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MX25L12833FZC-10G | 128 M-bit, 104 MHz max clock, no DTR support, lacks QPI mode, 3.0–3.6 V only | Lower bandwidth; unsuitable for XIP-critical designs requiring >133 MHz or DTR timing | Select only if DTR/QPI are unused and voltage margin above 3.0 V is guaranteed |
| S25FL128SAGMFI000 | 128 M-bit, 133 MHz, supports Octal DTR but requires different command set and pinout (16-pin SOIC) | Higher pin count and PCB footprint; incompatible with WSON-8 layout; needs driver rework | Consider only for new designs targeting Cypress' HyperBus ecosystem and higher density scaling paths |
Compared with MX25L12833FZC-10G and S25FL128SAGMFI000, the W25Q128JVFJM TR uniquely combines DTR-read capability, QPI mode, industrial-plus temperature range, and WSON-8 footprint - enabling compact, high-throughput, and field-upgradable embedded systems without layout or firmware overhaul.
Availability
W25Q128JVFJM TR is available at Aetrix Electronics and suitable for industrial automation controllers, automotive telematics modules, and medical diagnostic equipment requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for W25Q128JVFJM TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Winbond Electronics is a Taiwan-based semiconductor company specializing in specialty DRAM, mobile DRAM, and serial flash memory solutions since 1987.
The W25Q series targets embedded systems needing high-speed, low-power, and secure nonvolatile storage - designed specifically for code execution, firmware updates, and parameter retention in space-constrained industrial and automotive platforms.
FAQ
What is the package type and footprint of W25Q128JVFJM TR?
W25Q128JVFJM TR uses an 8-pin WSON 6×5-mm package (JEDEC MO-241AC) with exposed thermal pad. This matches Package Code P in Winbond's documentation and is distinct from SOIC-208, SOIC-300, or TFBGA variants. The pinout is identical to the W25Q128JV-DTR SOIC/WSON baseline, confirmed in Section 3.2 and 3.3 of the datasheet.
Does W25Q128JVFJM TR support Quad SPI and QPI modes?
Yes, W25Q128JVFJM TR supports both Quad SPI and QPI modes. Quad SPI requires setting the non-volatile Quad Enable (QE) bit in Status Register-2. QPI mode is entered via the 0x38 command and exited with 0xFF. Both modes use IO0–IO3 bidirectionally and are fully documented in Sections 6.1.3 and 6.1.4 of the datasheet.
How does the /HOLD pin function differ between Standard SPI and Quad SPI on W25Q128JVFJM TR?
In Standard SPI mode, /HOLD (Pin 7) pauses ongoing operations while /CS remains low. In Quad SPI mode, that same pin becomes IO3 and loses /HOLD functionality - confirmed in Notes 2 of Section 3.3 and Section 4.4. The W25Q128JVFJM TR datasheet explicitly states /HOLD is unavailable when QE=1.
What is the maximum clock frequency supported by W25Q128JVFJM TR in DTR mode?
W25Q128JVFJM TR supports DTR (Double Transfer Rate) read instructions up to 133 MHz clock frequency, achieving 266 MHz effective data rate in Dual I/O DTR and 532 MHz in Quad I/O DTR - specified in Section 1 (General Descriptions) and Table 9.6 (AC Electrical Characteristics).
Can W25Q128JVFJM TR be used for secure firmware storage with cryptographic key protection?
Yes, W25Q128JVFJM TR includes three 256-byte security registers with OTP lock bits (LB1–LB3), a 64-bit unique ID, and SFDP register support. Keys can be written once and permanently locked, preventing runtime readout - detailed in Sections 2 (Features), 7.1.9, and 8.2.31–8.2.34 of the datasheet.
W25Q128JVFJM TR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Winbond Electronics Corporation
- Series:
- SpiFlash®
- Package/Case:
- 16-SOIC (0.295", 7.50mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH - NOR
- Memory Size:
- 128Mbit
- Memory Organization:
- 16M x 8
- Memory Interface:
- SPI - Quad I/O, QPI, DTR
- Clock Frequency:
- 133 MHz
- Write Cycle Time - Word, Page:
- 3ms
- Access Time:
- -
- Voltage - Supply:
- 2.7V ~ 3.6V
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
W25Q128JVFJM TR FAQ
1.How can I place an order for W25Q128JVFJM TR through Aetrix?
Please submit a Request for Quotation (RFQ) for W25Q128JVFJM TR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for W25Q128JVFJM TR reliable?
The price and inventory of W25Q128JVFJM TR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for W25Q128JVFJM TR is usually 5 days.
3.What payment methods are accepted for W25Q128JVFJM TR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for W25Q128JVFJM TR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for W25Q128JVFJM TR?
W25Q128JVFJM TR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your W25Q128JVFJM TR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for W25Q128JVFJM TR?
For technical support, including W25Q128JVFJM TR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your W25Q128JVFJM TR requirements.
6.How does Aetrix verify that W25Q128JVFJM TR is sourced from the original manufacturer or authorized distributors?
All W25Q128JVFJM TR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that W25Q128JVFJM TR meets industry standards.
7.What is the process for return or replacement of W25Q128JVFJM TR?
All W25Q128JVFJM TR units undergo pre-shipment inspection (PSI). If there is an issue with W25Q128JVFJM TR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The W25Q128JVFJM TR part is unused and in its original packaging.
Return procedure for W25Q128JVFJM TR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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