Winbond Electronics Corporation W25Q128JVFJQ TR
- Part No.:
- W25Q128JVFJQ TR
- Manufacturer:
- Winbond Electronics Corporation
- Category:
- Memory
- Package:
- 16-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
W25Q128JVFJQ TR.pdf
- Description:
- IC FLASH 128MBIT SPI/QUAD 16SOIC
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
W25Q128JVFJQ TR from Winbond is a 3.3V, 128M-bit (16MB) serial NOR flash memory with Dual/Quad SPI interface, organized as 65,536 × 256-byte pages and supporting 4KB sector, 32KB/64KB block, and chip erase. It delivers up to 133MHz SPI clock rate (532MHz Quad I/O equivalent), <1µA power-down current, and operates from −40°C to +105°C - used for code XIP, firmware storage, and boot image retention in industrial controllers.
For engineers reviewing the W25Q128JVFJQ TR datasheet, W25Q128JVFJQ TR pinout, W25Q128JVFJQ TR application, or W25Q128JVFJQ TR equivalent, key selection criteria include Quad Enable (QE) bit configuration, /HOLD vs /RESET pin availability per package, 4KB sector granularity for parameter storage, and JEDEC SFDP register support for auto-configuration.
Technical Context
The W25Q128JVFJQ TR implements a standard SPI-compatible command set extended with Dual/Quad I/O modes enabled via non-volatile QE bit in Status Register-2. Its architecture supports true execute-in-place (XIP) operation using Fast Read Quad I/O (EBh) with wrap-length configurable for 8/16/32/64-byte bursts.
It integrates three 256-byte security registers with OTP locks, 64-bit unique ID, and hardware write protection via /WP pin combined with volatile/non-volatile status bits (BP2–BP0, TB, SEC, CMP). The /RESET pin is dedicated and functional only in SOIC-16 and TFBGA packages - absent in 8-pin SOIC and WSON variants like W25Q128JVFJQ TR.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 128 M-bit (16 MB) - supports full firmware images for mid-tier microcontrollers without external memory expansion. |
| Interface | Dual/Quad SPI - enables 266 MB/s (Dual) or 532 MB/s (Quad) effective throughput using IO0–IO3 pins when QE=1. |
| Operating Voltage | 2.7 V to 3.6 V - compatible with 3.3 V logic systems; no level-shifting required for host MCU SPI peripherals. |
| Temperature Range | −40°C to +105°C - qualified for Industrial Plus grade applications including motor drives and PLCs. |
| Erase Granularity | Uniform 4 KB sectors (4,096 total) - allows fine-grained firmware update partitioning and parameter storage without erasing code regions. |
| Endurance & Retention | 100,000 program/erase cycles per sector; >20-year data retention - suitable for field-upgradable embedded systems with infrequent writes. |
| Power-Down Current | 1 µA (typ.) - enables ultra-low-power sleep modes in battery-backed or energy-harvesting designs. |
Pinout & Package
W25Q128JVFJQ TR uses an 8-pin SOIC 208-mil (Package Code S) with exposed pad, pin-compatible with legacy W25Q128FV devices. Pin 7 is /HOLD (not /RESET); /RESET is not available in this package variant.
| Pin | Circuit Role | Design Meaning |
|---|---|---|
| 1 (/CS) | Chip Select Input | Active-low enable; high-impedance DO during deselect; must transition high→low after power-up before first instruction. |
| 2 (DO / IO1) | Data Output / Quad I/O | Unidirectional output in Standard SPI; bidirectional I/O1 in Dual/Quad mode when QE=1. |
| 3 (/WP / IO2) | Write Protect Input / Quad I/O | Hardware lock for status register; becomes IO2 in Quad mode when QE=1; active-low. |
| 4 (GND) | Ground Reference | Primary return path for VCC and I/O signals; requires low-impedance PCB connection to minimize noise coupling. |
| 5 (DI / IO0) | Data Input / Quad I/O | Unidirectional input in Standard SPI; bidirectional I/O0 in Dual/Quad mode when QE=1. |
| 6 (CLK) | Serial Clock Input | Edge-triggered timing reference; supports Mode 0 and Mode 3; max 133 MHz frequency. |
| 7 (/HOLD / IO3) | Hold Input / Quad I/O | Pauses ongoing read/write; becomes IO3 in Quad mode when QE=1; not functional as /RESET. |
| 8 (VCC) | Power Supply | 2.7–3.6 V supply; decoupling capacitor (0.1 µF) required within 5 mm of pin per datasheet layout guidelines. |
Key Features
| Feature | Design Value |
|---|---|
| Quad Enable (QE) bit | Non-volatile bit in Status Register-2 that reassigns /WP and /HOLD to IO2/IO3 - required to activate Quad SPI mode without hardware change. |
| Continuous Read with Wrap | Configurable 8/16/32/64-byte burst wrap reduces address overhead and enables deterministic XIP latency for real-time code execution. |
| Security Registers | Three 256-byte OTP-lockable registers - store cryptographic keys or calibration data with hardware-enforced write protection. |
| SFDP Register Support | JEDEC JESD216-compliant Serial Flash Discoverable Parameters - allows host bootloader to auto-detect density, timing, and command set without hard-coded assumptions. |
| Erase/Program Suspend | Allows pausing long erase/program operations to service time-critical interrupts - critical for deterministic real-time firmware updates. |
Applications
| Industrial PLC Firmware Storage | Automotive ADAS Boot Image |
|---|---|
|
Use Scenario: Storing and executing boot firmware and runtime logic in programmable logic controllers deployed in factory automation environments. IC Role / Device Role / Timing Role: Primary non-volatile code storage with XIP capability; provides deterministic read latency under -40°C to +105°C thermal cycling. Use Value: Eliminates need for parallel NOR flash or external RAM loading; 4KB sector erase enables safe over-the-air (OTA) partial updates without disrupting control loop execution. |
Use Scenario: Holding boot code and sensor fusion algorithms for automotive camera/radar ECUs requiring AEC-Q100 alignment and fast cold-start performance. IC Role / Device Role / Timing Role: Secure, high-reliability boot memory with 64-bit unique ID for device authentication and SFDP-driven initialization. Use Value: Supports ASIL-B compliant boot integrity checks via security registers; Quad SPI read speeds reduce boot time by >40% versus standard SPI alternatives. |
| Medical Device Configuration Data | Networking Equipment Image Backup |
|
Use Scenario: Retaining calibrated sensor offsets, user preferences, and regulatory audit logs in portable diagnostic instruments with battery backup. IC Role / Device Role / Timing Role: Parameter storage with hardware write protection (/WP pin + BP bits) and >20-year data retention at elevated ambient temperatures. Use Value: Prevents accidental or malicious overwrite of safety-critical calibration data; 100K-cycle endurance ensures reliability across 10+ years of clinical use. |
Use Scenario: Mirroring primary boot images in enterprise switches and routers to enable fail-safe recovery after corrupted firmware uploads. IC Role / Device Role / Timing Role: Redundant firmware repository accessed via SPI bus; leverages chip erase (C7h) for atomic image replacement. Use Value: Enables zero-downtime firmware rollback; dual-plane architecture allows background erase while serving active image - no service interruption during maintenance. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial NOR flash memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MX25L12833FZNI-10G | 1.8 V core voltage; 104 MHz max clock; no /HOLD pin; lacks SFDP and security registers. | Targeted at low-power portable devices; unsuitable for industrial temperature or secure boot use cases. | Select only if system operates at 1.8 V and does not require Quad I/O, suspend/resume, or hardware security features. |
| S25FL128SAGMFI000 | 3 V supply; 133 MHz clock; includes HyperBus interface option; larger 16-pin SOIC package with dedicated /RESET. | Designed for high-bandwidth applications needing >532 MB/s throughput or dual-interface flexibility (SPI + HyperBus). | Choose when board layout accommodates larger footprint and system requires either HyperBus compatibility or guaranteed hardware /RESET functionality. |
Compared with W25Q128JVFJQ TR, MX25L12833FZNI-10G offers lower voltage operation but sacrifices industrial temperature range, security, and Quad SPI configurability; S25FL128SAGMFI000 adds interface flexibility and reset reliability at the cost of package size and design complexity.
Availability
W25Q128JVFJQ TR is available at Aetrix Electronics and suitable for industrial automation, automotive ADAS modules, and medical diagnostics equipment requiring stable component supply across extended temperature ranges and long product lifecycles.
Supply support for W25Q128JVFJQ TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Winbond Electronics is a Taiwan-based semiconductor company specializing in specialty memory solutions, including serial NOR/NAND flash and mobile DRAM, with global manufacturing and quality certifications.
The W25Q series targets high-performance, space-constrained embedded systems requiring reliable code storage, fast XIP execution, and robust security - designed specifically for industrial, automotive, and networking applications demanding extended temperature operation and long-term data integrity.
FAQ
What is the package type and pin count of W25Q128JVFJQ TR?
W25Q128JVFJQ TR uses an 8-pin SOIC 208-mil (Package Code S) with gull-wing leads and internal exposed pad. It has no /RESET pin - Pin 7 functions exclusively as /HOLD (or IO3 in Quad mode), distinguishing it from SOIC-16 and TFBGA variants of the W25Q128JV family.
Does W25Q128JVFJQ TR support Quad SPI mode, and how is it enabled?
Yes, W25Q128JVFJQ TR supports Quad SPI mode via Fast Read Quad I/O (EBh) and Quad Input Page Program (32h) instructions. Activation requires setting the non-volatile Quad Enable (QE) bit in Status Register-2 using Write Status Register-2 (31h), which reassigns /WP and /HOLD pins to IO2 and IO3 respectively.
What is the maximum SPI clock frequency supported by W25Q128JVFJQ TR?
W25Q128JVFJQ TR supports up to 133 MHz for single-data-rate SPI operations. In Dual SPI mode (e.g., Fast Read Dual I/O), this yields an effective 266 MB/s transfer rate; in Quad SPI mode (e.g., Fast Read Quad I/O), it achieves up to 532 MB/s - verified under industrial temperature conditions per datasheet AC characteristics.
How does hardware write protection work on W25Q128JVFJQ TR?
Hardware write protection on W25Q128JVFJQ TR combines the active-low /WP pin with status register bits (BP2–BP0, TB, SEC, CMP). When /WP is held low, writes to the status register are blocked unless SRP=0 and SRL=0. This prevents accidental or malicious modification of sector/block protection settings during operation.
Is W25Q128JVFJQ TR suitable for execute-in-place (XIP) applications?
Yes, W25Q128JVFJQ TR is explicitly designed for XIP operation using Fast Read Quad I/O (EBh) with configurable burst wrap (8/16/32/64 bytes). Its 133 MHz clock and low-latency continuous read eliminate bottlenecks in real-time code execution directly from flash, validated across −40°C to +105°C.
W25Q128JVFJQ TR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Winbond Electronics Corporation
- Series:
- SpiFlash®
- Package/Case:
- 16-SOIC (0.295", 7.50mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH - NOR
- Memory Size:
- 128Mbit
- Memory Organization:
- 16M x 8
- Memory Interface:
- SPI - Quad I/O, QPI, DTR
- Clock Frequency:
- 133 MHz
- Write Cycle Time - Word, Page:
- 3ms
- Access Time:
- -
- Voltage - Supply:
- 2.7V ~ 3.6V
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
W25Q128JVFJQ TR FAQ
1.How can I place an order for W25Q128JVFJQ TR through Aetrix?
Please submit a Request for Quotation (RFQ) for W25Q128JVFJQ TR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for W25Q128JVFJQ TR reliable?
The price and inventory of W25Q128JVFJQ TR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for W25Q128JVFJQ TR is usually 5 days.
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Once your W25Q128JVFJQ TR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
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For technical support, including W25Q128JVFJQ TR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your W25Q128JVFJQ TR requirements.
6.How does Aetrix verify that W25Q128JVFJQ TR is sourced from the original manufacturer or authorized distributors?
All W25Q128JVFJQ TR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that W25Q128JVFJQ TR meets industry standards.
7.What is the process for return or replacement of W25Q128JVFJQ TR?
All W25Q128JVFJQ TR units undergo pre-shipment inspection (PSI). If there is an issue with W25Q128JVFJQ TR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The W25Q128JVFJQ TR part is unused and in its original packaging.
Return procedure for W25Q128JVFJQ TR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
W25Q128JVFJQ TR Tags

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M24C02-WMN6TP
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AT24C02C-XHM-T
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AT21CS01-STUM10-T
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M24C02-FMC6TG
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93LC46BT-I/OT
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AT24C04C-SSHM-T
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