Winbond Electronics Corporation W25Q128JVPJM TR
- Part No.:
- W25Q128JVPJM TR
- Manufacturer:
- Winbond Electronics Corporation
- Category:
- Memory
- Package:
- 8-WDFN Exposed Pad
- Datasheet:
-
W25Q128JVPJM TR.pdf
- Description:
- IC FLASH 128MBIT SPI/QUAD 8WSON
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
W25Q128JVPJM TR from Winbond is a 128M-bit (16MB) serial NOR flash memory IC supporting Dual/Quad SPI, QPI, and DTR read modes. It operates from 2.7V to 3.6V, delivers up to 133MHz SPI clock rate (532MHz equivalent Quad I/O), features uniform 4KB sectors, 100K program-erase cycles per sector, and 20+ year data retention. It is used for XIP code execution, firmware storage, and parameter logging in space-constrained industrial controllers.
For engineers reviewing the W25Q128JVPJM TR datasheet, W25Q128JVPJM TR pinout, W25Q128JVPJM TR application, or W25Q128JVPJM TR equivalent, key selection criteria include Quad Enable (QE) bit configuration, /HOLD vs /RESET pin availability in 8-pin WSON, DTR timing compliance, and sector protection granularity for secure firmware updates.
Technical Context
The W25Q128JVPJM TR implements a flexible SPI-compatible interface with mode-selectable operation: Standard SPI (DI/DO), Dual SPI (IO0/IO1), Quad SPI (IO0–IO3), and QPI (all four IOs as bidirectional). Its command set includes DTR Fast Read (0Dh, BDh, EDh) requiring precise setup/hold timing on CLK and /CS relative to data valid windows.
Internally, it uses a 65,536-page (256-byte/page) array organized into 4,096 × 4KB sectors and 256 × 64KB blocks. Erase suspend/resume, programmable output drive strength (DRV1/DRV0), and volatile/non-volatile status register bits (e.g., QE, TB, BP2–BP0) enable fine-grained control over memory access and protection during concurrent operations.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 128 M-bit (16 MB), organized as 65,536 × 256-byte pages |
| Supply Voltage | 2.7 V to 3.6 V - enables direct integration with 3.3 V logic without level shifting |
| Max Clock Frequency | 133 MHz SPI; supports 266 MHz (Dual I/O) and 532 MHz (Quad I/O) effective throughput |
| Erase Endurance | 100,000 program-erase cycles per sector - suitable for frequent firmware update partitions |
| Data Retention | 20+ years at +85°C - validated for long-life industrial deployments |
| Operating Temp | −40°C to +105°C - qualified for Industrial Plus grade applications |
| Read Throughput | 66 MB/s continuous burst - achieved via DTR Quad I/O with wrap mode |
Pinout & Package
W25Q128JVPJM TR is supplied in an 8-pad WSON package (6 mm × 5 mm, Package Code P), with exposed thermal pad. Pin functions are shared across SPI modes: IO0–IO3 serve as DI/DO in standard mode, and as bidirectional data lines in Dual/Quad/QPI modes when Quad Enable (QE) is set.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 /CS | Chip Select Input | Active-low enable; must transition high→low before instruction acceptance; controls DO high-impedance state |
| 2 DO (IO1) | Data Output / I/O1 | Unidirectional output in Standard SPI; bidirectional I/O in Dual/Quad/QPI modes |
| 3 /WP (IO2) | Write Protect Input / I/O2 | Hardware lock for status register; repurposed as IO2 when QE=1; not available in Quad mode |
| 4 GND | Ground Reference | Primary return path for VCC and I/O signals; connects to thermal pad for thermal dissipation |
| 5 DI (IO0) | Data Input / I/O0 | Unidirectional input in Standard SPI; bidirectional I/O in Dual/Quad/QPI modes |
| 6 CLK | Serial Clock Input | Edge-triggered timing reference; supports Mode 0 and Mode 3 SPI polarity/phase |
| 7 /HOLD or /RESET (IO3) | Hold/Reset Input / I/O3 | Active-low pause signal; configurable as /RESET only when QE=0 in 8-pin packages; becomes IO3 when QE=1 |
| 8 VCC | Power Supply | Single 2.7–3.6 V supply; powers core, I/O, and charge pumps for erase/program |
Key Features
| Feature | Design Value |
|---|---|
| Dual/Quad SPI & QPI Support | Enables scalable bandwidth: 133 MHz single-line, 266 MHz dual-line, 532 MHz quad-line, and reduced instruction overhead in QPI mode |
| DTR Read Capability | Double Transfer Rate instructions (0Dh/BDh/EDh) double data rate per clock edge - critical for meeting real-time XIP latency budgets |
| Uniform 4KB Sector Architecture | Allows independent erasure of firmware partitions, configuration tables, or log buffers without disturbing adjacent data |
| Erase/Program Suspend & Resume | Permits background erase or program to be paused for urgent reads - essential for deterministic response in RTOS environments |
| Three 256-Byte Security Registers | OTP-lockable storage for cryptographic keys or calibration data - isolated from main array and protected by LB1–LB3 bits |
Applications
| Industrial PLC Firmware Storage | Medical Device Boot Image |
|---|---|
Use Scenario: Storing boot firmware and field-upgradable application code in a DIN-rail mounted PLC with limited PCB area and no external RAM. IC Role / Device Role / Timing Role: Primary non-volatile code storage enabling Execute-in-Place (XIP) directly from Quad SPI bus at ≤532 Mbps effective rate. Use Value: Eliminates need for parallel NOR or external RAM buffer; reduces BOM count and power by leveraging 1µA deep power-down current. | Use Scenario: Securing boot image integrity and storing device-specific calibration parameters in Class II medical imaging equipment. IC Role / Device Role / Timing Role: Trusted firmware repository with hardware write-protection (/WP pin + BP bits) and OTP-locked security registers for keys. Use Value: Meets IEC 62304 software safety requirements via immutable sector locking and 20-year data retention at +85°C. |
| Automotive ADAS Camera Module | Smart Energy Meter Firmware |
Use Scenario: Holding camera ISP firmware and runtime configuration in a compact automotive vision module operating at −40°C to +105°C. IC Role / Device Role / Timing Role: High-reliability flash with Industrial Plus temperature rating and DTR read for low-latency sensor initialization sequences. Use Value: Guarantees startup timing compliance under thermal stress; supports seamless firmware patching via sector-level erase without full chip erase. | Use Scenario: Storing tariff tables, communication stack binaries, and tamper logs in utility-grade smart meters deployed in outdoor enclosures. IC Role / Device Role / Timing Role: Secure, long-life data logger with individual sector lock (36h/39h) and SFDP register for dynamic parameter discovery. Use Value: Enables remote firmware updates with atomic sector writes and cryptographic signature verification using dedicated security registers. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial NOR flash applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MX25L12833FZNI-08G | 128Mb, 3.3V, 104MHz max clock, no DTR support, SOIC/WSON/TFBGA packages | Lacks DTR read modes and QPI; lower max throughput (≤416 Mbps Quad); no /RESET pin in 8-pin WSON | Choose when DTR timing margins are non-critical and legacy SPI controller compatibility is prioritized over peak bandwidth. |
| S25FL128SAGMFI000 | 128Mb, 3.0V, 133MHz clock, supports DTR but requires separate /RESET pin; only in 16-pin SOIC and TFBGA | Requires 16-pin footprint or TFBGA; no 8-pin WSON option; /RESET is dedicated (not multiplexed with /HOLD) | Select when hardware reset independence is mandatory and board layout allows larger package or ball grid array. |
Compared with MX25L12833FZNI-08G and S25FL128SAGMFI000, the W25Q128JVPJM TR uniquely combines 8-pin WSON packaging, DTR-enabled 532 Mbps Quad I/O, and multiplexed /HOLD//RESET functionality - delivering highest density-per-mm² and lowest latency for XIP in thermally constrained industrial designs.
Availability
W25Q128JVPJM TR is available at Aetrix Electronics and suitable for industrial automation, medical diagnostics, and automotive ADAS applications requiring stable component supply, extended temperature operation, and secure firmware storage.
Supply support for W25Q128JVPJM TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Winbond Electronics is a Taiwan-based semiconductor company specializing in specialty DRAM, mobile DRAM, and serial flash memory solutions for industrial, automotive, and consumer markets.
The W25Q128JVPJM TR belongs to Winbond's W25Q "SpiFlash" family, designed specifically for high-performance, secure, and space-efficient code and data storage in resource-constrained embedded systems.
FAQ
What is the package type and footprint of the W25Q128JVPJM TR?
The W25Q128JVPJM TR uses an 8-pad WSON package measuring 6 mm × 5 mm (Package Code P) with an exposed thermal pad. It shares pinout compatibility with other W25Q128JV variants in the same package, including identical /CS, CLK, DI (IO0), DO (IO1), /WP (IO2), /HOLD or /RESET (IO3), GND, and VCC assignments. This footprint is widely supported in industrial PCB design libraries.
Does the W25Q128JVPJM TR support Quad Peripheral Interface (QPI) mode?
Yes, the W25Q128JVPJM TR supports QPI mode via the 38h instruction, enabling all four IO pins (IO0–IO3) to operate bidirectionally with reduced instruction overhead. QPI mode requires the non-volatile Quad Enable (QE) bit in Status Register-2 to be set. Once enabled, /WP and /HOLD pins become IO2 and IO3 respectively, and standard SPI commands are no longer accepted until QPI is exited using FFh.
How does the /HOLD pin function differ from the /RESET pin on the W25Q128JVPJM TR?
On the W25Q128JVPJM TR (8-pin WSON), pin 7 serves as /HOLD or /RESET depending on the HOLD/RST bit in Status Register-3 and the QE bit setting. When QE = 0, it functions as /HOLD (active-low pause); when QE = 1, it becomes IO3 and /HOLD is disabled. Unlike 16-pin SOIC or TFBGA packages, this 8-pin variant has no dedicated /RESET pin - hardware reset requires software reset (66h + 99h) or power cycle.
What is the significance of DTR (Double Transfer Rate) support in the W25Q128JVPJM TR?
DTR support in the W25Q128JVPJM TR enables two data transitions per clock cycle (on both rising and falling edges) for read operations like DTR Fast Read (0Dh), DTR Dual I/O (BDh), and DTR Quad I/O (EDh). This doubles effective data rate versus standard SDR mode, achieving up to 66 MB/s continuous throughput - critical for real-time XIP execution where instruction fetch latency must be minimized.
Can the W25Q128JVPJM TR be used for secure key storage?
Yes, the W25Q128JVPJM TR includes three 256-byte Security Registers with One-Time-Programmable (OTP) lock bits (LB1–LB3). Once locked, these registers cannot be rewritten or read back, making them suitable for storing cryptographic keys, device certificates, or calibration secrets. Access requires specific instructions (42h/48h/44h), and protection is enforced independently of main array write protection settings.
W25Q128JVPJM TR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Winbond Electronics Corporation
- Series:
- SpiFlash®
- Package/Case:
- 8-WDFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH - NOR
- Memory Size:
- 128Mbit
- Memory Organization:
- 16M x 8
- Memory Interface:
- SPI - Quad I/O, QPI, DTR
- Clock Frequency:
- 133 MHz
- Write Cycle Time - Word, Page:
- 3ms
- Access Time:
- -
- Voltage - Supply:
- 2.7V ~ 3.6V
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-WSON (6x5)
W25Q128JVPJM TR FAQ
1.How can I place an order for W25Q128JVPJM TR through Aetrix?
Please submit a Request for Quotation (RFQ) for W25Q128JVPJM TR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for W25Q128JVPJM TR reliable?
The price and inventory of W25Q128JVPJM TR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for W25Q128JVPJM TR is usually 5 days.
3.What payment methods are accepted for W25Q128JVPJM TR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for W25Q128JVPJM TR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for W25Q128JVPJM TR?
W25Q128JVPJM TR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your W25Q128JVPJM TR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for W25Q128JVPJM TR?
For technical support, including W25Q128JVPJM TR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your W25Q128JVPJM TR requirements.
6.How does Aetrix verify that W25Q128JVPJM TR is sourced from the original manufacturer or authorized distributors?
All W25Q128JVPJM TR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that W25Q128JVPJM TR meets industry standards.
7.What is the process for return or replacement of W25Q128JVPJM TR?
All W25Q128JVPJM TR units undergo pre-shipment inspection (PSI). If there is an issue with W25Q128JVPJM TR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The W25Q128JVPJM TR part is unused and in its original packaging.
Return procedure for W25Q128JVPJM TR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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