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Home > Products > Integrated Circuits (ICs) > Memory > Memory

Winbond Electronics Corporation W25Q128JVPJQ TR

Name: W25Q128JVPJQ TR
Brand: Winbond Electronics Corporation
SKU: W25Q128JVPJQ TR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: W25Q128JVPJQ TR

Manufacturer:: Winbond Electronics Corporation

Category:: Memory

Package:: 8-WDFN Exposed Pad

Datasheet:: W25Q128JVPJQ TR.pdf

Description:: IC FLASH 128MBIT SPI/QUAD 8WSON

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Product details

Overview

W25Q128JVPJQ TR from Winbond is a 128M-bit (16MB) serial NOR flash memory with Dual/Quad SPI interface, organized into 65,536 pages of 256 bytes each and supporting 4KB sector, 32KB block, 64KB block, and chip erase. It operates from 2.7V to 3.6V, draws ≤1 µA in power-down mode, and delivers up to 133 MHz SPI clock frequency (532 MHz equivalent Quad I/O), enabling XIP execution in industrial embedded systems.

For engineers reviewing the W25Q128JVPJQ TR datasheet, W25Q128JVPJQ TR pinout, W25Q128JVPJQ TR application, or W25Q128JVPJQ TR equivalent, key selection considerations include its 8-pin SOIC 208-mil (Package Code S) footprint, hardware /WP and /HOLD support, Quad Enable (QE) bit configuration, and JEDEC-compliant SFDP register for auto-configuration in boot-critical firmware storage.

Technical Context

The W25Q128JVPJQ TR implements a standard SPI Mode 0/3 interface with bidirectional IO0–IO3 pins enabled via non-volatile QE bit in Status Register-2. Its command set includes Fast Read Quad I/O (EBh), Quad Input Page Program (32h), and Erase/Program Suspend (75h), enabling deterministic latency control during concurrent firmware updates and real-time code execution.

It integrates three 256-byte Security Registers with OTP locks, 64-bit Unique ID, and configurable write protection using volatile/non-volatile BP2–BP0, TB, SEC, CMP, and SRP bits - all accessible via dedicated instructions (e.g., 42h/44h/48h) without requiring external logic.

Key Specifications

Parameter	Value and Actual Design Meaning
Memory Density	128 M-bit (16 MB), directly addressable across 24-bit space for full firmware image storage
Interface Protocol	Dual/Quad SPI with JEDEC SFDP support - enables automatic driver initialization and timing parameter discovery
Max Clock Frequency	133 MHz single I/O; 266 MHz dual I/O; 532 MHz quad I/O - sustains ≥66 MB/s continuous read throughput
Erase Granularity	Uniform 4 KB sectors (4,096 total), 32 KB blocks (2,048), 64 KB blocks (256) - supports fine-grained OTA update partitioning
Endurance & Retention	100,000 program/erase cycles per sector; >20 years data retention at +85°C - validated for industrial lifecycle requirements
Operating Voltage	2.7 V to 3.6 V - compatible with 3.3 V logic rails and brown-out tolerant power domains
Temperature Range	−40°C to +85°C (Industrial Grade) - qualified per AEC-Q100 stress test conditions for automotive ECUs

Pinout & Package

W25Q128JVPJQ TR uses the 8-pin SOIC 208-mil package (Package Code S), with exposed pad not present and no /RESET pin - hardware reset is software-only via 66h/99h sequence.

Pin/Terminal	Circuit Role	Design Meaning
1 /CS	Chip Select Input	Active-low enable; must transition high→low after power-up before first instruction; high-impedance DO when deasserted
2 DO (IO1)	Data Output / Quad I/O 1	Unidirectional output in Standard SPI; bidirectional I/O1 in Dual/Quad modes; requires QE=1 for Quad use
3 /WP (IO2)	Write Protect Input / Quad I/O 2	Hardware lock for Status Register; becomes IO2 when QE=1 - enables full Quad I/O bus utilization
4 GND	Ground Reference	Primary return path for VCC and I/O signals; decoupling capacitor must be placed adjacent to this pin
5 DI (IO0)	Data Input / Quad I/O 0	Unidirectional input in Standard SPI; bidirectional I/O0 in Dual/Quad modes; used for all instruction/address loading
6 CLK	Serial Clock Input	Edge-triggered timing reference; supports Mode 0 (CLK idle low) and Mode 3 (CLK idle high); max 133 MHz
7 /HOLD (IO3)	Hold Input / Quad I/O 3	Pauses ongoing transfer without deselecting device; becomes IO3 when QE=1 - required for full Quad operation
8 VCC	Power Supply	2.7–3.6 V supply; bypassed with 100 nF ceramic capacitor near pin; powers internal HV generators for erase/program

Key Features

Feature	Design Value
Quad Enable (QE) Bit	Non-volatile bit in Status Register-2 that reassigns /WP and /HOLD to IO2/IO3 - essential for enabling full 4-line data bus
Erase/Program Suspend	75h/7Ah instructions allow pausing long erase/program operations to service time-critical reads - critical for real-time systems
Security Registers	Three 256-byte OTP-lockable registers (42h/44h/48h) for storing keys, calibration data, or secure boot manifests
64-bit Unique ID	Factory-programmed immutable serial number (4Bh instruction) - enables device-level traceability and license binding
Continuous Read Wrap	77h instruction configures 8/16/32/64-byte wrap boundaries - eliminates address overflow checks during streaming reads

Applications

Industrial PLC Firmware Storage	Automotive ADAS Boot Memory
Use Scenario: Storing and executing boot firmware and safety-critical application code in programmable logic controllers operating continuously in harsh factory environments. IC Role / Device Role / Timing Role: Primary non-volatile code storage with XIP capability via Fast Read Quad I/O (EBh), delivering deterministic <100 ns access latency for real-time task scheduling. Use Value: 4KB sector granularity enables atomic firmware patching without disrupting runtime logic; 100K-cycle endurance ensures >10-year field reliability under frequent OTA updates.	Use Scenario: Holding boot ROM, sensor fusion algorithms, and ASIL-B compliant diagnostic routines in camera/radar ECUs where startup time and data integrity are safety-critical. IC Role / Device Role / Timing Role: Secure boot source authenticated via SFDP-managed configuration and 64-bit Unique ID (4Bh), with hardware write-protection (/WP) preventing accidental corruption during voltage transients. Use Value: −40°C to +85°C rating and >20-year data retention meet ISO 26262 requirements; Security Registers (42h/44h/48h) store cryptographic keys isolated from main array.
Medical Imaging System Configuration	Smart Energy Meter Data Logging
Use Scenario: Retaining calibrated imaging parameters, user preferences, and regulatory audit logs across power cycles in portable ultrasound and X-ray devices. IC Role / Device Role / Timing Role: Parameter storage with individual sector lock (36h/39h) - isolates calibration data from firmware updates while allowing independent field recalibration. Use Value: Top/Bottom Block Protect (TB bit) and Complement Protect (CMP) prevent unauthorized overwrite of FDA-mandated calibration records; <1 µA power-down current extends battery life.	Use Scenario: Recording time-stamped energy consumption metrics, tariff schedules, and tamper-event logs in ANSI C12.22-compliant smart meters deployed in unattended outdoor locations. IC Role / Device Role / Timing Role: High-reliability data logger using 32KB block erase (52h) for daily log rotation and Erase Suspend (75h) to avoid missing pulse interrupts during long erase cycles. Use Value: 100K-cycle endurance supports >27 years of daily 32KB erases; SFDP register auto-configures timing for varying temperature-induced clock drift across −40°C to +85°C range.

Industrial PLC Firmware Storage

Automotive ADAS Boot Memory

Use Scenario: Storing and executing boot firmware and safety-critical application code in programmable logic controllers operating continuously in harsh factory environments.

IC Role / Device Role / Timing Role: Primary non-volatile code storage with XIP capability via Fast Read Quad I/O (EBh), delivering deterministic <100 ns access latency for real-time task scheduling.

Use Value: 4KB sector granularity enables atomic firmware patching without disrupting runtime logic; 100K-cycle endurance ensures >10-year field reliability under frequent OTA updates.

Use Scenario: Holding boot ROM, sensor fusion algorithms, and ASIL-B compliant diagnostic routines in camera/radar ECUs where startup time and data integrity are safety-critical.

IC Role / Device Role / Timing Role: Secure boot source authenticated via SFDP-managed configuration and 64-bit Unique ID (4Bh), with hardware write-protection (/WP) preventing accidental corruption during voltage transients.

Use Value: −40°C to +85°C rating and >20-year data retention meet ISO 26262 requirements; Security Registers (42h/44h/48h) store cryptographic keys isolated from main array.

Medical Imaging System Configuration

Smart Energy Meter Data Logging

Use Scenario: Retaining calibrated imaging parameters, user preferences, and regulatory audit logs across power cycles in portable ultrasound and X-ray devices.

IC Role / Device Role / Timing Role: Parameter storage with individual sector lock (36h/39h) - isolates calibration data from firmware updates while allowing independent field recalibration.

Use Value: Top/Bottom Block Protect (TB bit) and Complement Protect (CMP) prevent unauthorized overwrite of FDA-mandated calibration records; <1 µA power-down current extends battery life.

Use Scenario: Recording time-stamped energy consumption metrics, tariff schedules, and tamper-event logs in ANSI C12.22-compliant smart meters deployed in unattended outdoor locations.

IC Role / Device Role / Timing Role: High-reliability data logger using 32KB block erase (52h) for daily log rotation and Erase Suspend (75h) to avoid missing pulse interrupts during long erase cycles.

Use Value: 100K-cycle endurance supports >27 years of daily 32KB erases; SFDP register auto-configures timing for varying temperature-induced clock drift across −40°C to +85°C range.

Equivalent & Alternatives

The following parts are listed as comparable options for similar serial NOR flash applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
MX25L12833FZC-10G	128Mb, 104 MHz max clock, SOIC 208-mil, no /HOLD pin, no SFDP register	Lacks Quad I/O suspend/resume and JEDEC SFDP - requires hardcoded timing in bootloader	Choose when cost sensitivity outweighs configurability needs and Quad I/O bandwidth is unused
S25FL128SAGMFI000	128Mb, 80 MHz max clock, SOIC 208-mil, includes /RESET pin, supports HyperBus interface	Lower bandwidth; adds hardware /RESET but lacks 64-bit UID and Security Registers	Prefer when system-level reset coordination is mandatory and security features are secondary

Compared with MX25L12833FZC-10G and S25FL128SAGMFI000, W25Q128JVPJQ TR provides higher throughput (133 MHz vs ≤104 MHz), built-in SFDP for plug-and-play timing adaptation, and dedicated security primitives - making it optimal for safety-certified, field-upgradable embedded systems.

Availability

W25Q128JVPJQ TR is available at Aetrix Electronics and suitable for industrial PLC firmware storage, automotive ADAS boot memory, and medical imaging system configuration requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for W25Q128JVPJQ TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Winbond Electronics is a Taiwan-based semiconductor manufacturer specializing in specialty DRAM, mobile DRAM, and serial flash memory solutions for industrial, automotive, and consumer markets.

The W25Q series targets high-performance, secure, and flexible code and data storage in resource-constrained embedded systems - emphasizing XIP capability, robust write protection, and JEDEC-standard interoperability.

FAQ

Does W25Q128JVPJQ TR support hardware reset?

No, W25Q128JVPJQ TR does not support hardware reset. The /RESET pin is absent in its 8-pin SOIC 208-mil (Package Code S) configuration. Reset functionality is software-only via the Enable Reset (66h) followed by Reset Device (99h) instruction sequence, which takes ~30 µs to complete. This behavior is explicitly defined in the datasheet for Package Code S variants.

What is the function of the /HOLD pin on W25Q128JVPJQ TR?

On W25Q128JVPJQ TR, the /HOLD pin (Pin 7) serves as a pause control: when asserted low while /CS is active, it places DO in high-impedance state and ignores DI/CLK transitions, preserving internal state. When QE=1 for Quad SPI, this pin becomes IO3 - so /HOLD is only available in Standard/Dual SPI modes. Its active-low assertion requires no external pull-up per datasheet recommendations.

How is Quad SPI enabled on W25Q128JVPJQ TR?

Quad SPI is enabled on W25Q128JVPJQ TR by setting the Quad Enable (QE) bit in Status Register-2 using Write Status Register-2 (31h) instruction. Once QE=1, /WP (Pin 3) and /HOLD (Pin 7) become IO2 and IO3 respectively, completing the 4-line I/O bus. The device then accepts Quad-specific instructions like Fast Read Quad I/O (EBh). QE is non-volatile and persists across power cycles unless cleared.

Can W25Q128JVPJQ TR execute code directly from flash (XIP)?

Yes, W25Q128JVPJQ TR supports true execute-in-place (XIP) operation via Fast Read Quad I/O (EBh) and Continuous Read with Wrap (77h). Its 133 MHz clock and 532 MHz equivalent Quad bandwidth deliver sustained >66 MB/s read throughput - sufficient for real-time code execution without shadowing to RAM. XIP is validated across the full −40°C to +85°C temperature range.

What write protection mechanisms does W25Q128JVPJQ TR provide?

W25Q128JVPJQ TR provides layered write protection: hardware /WP pin (active-low) locks Status Register writes; non-volatile BP2–BP0, TB, SEC, CMP, and SRP bits configure sector/block-level protection; and OTP-locked Security Registers (42h/44h/48h) isolate sensitive data. All mechanisms operate independently and can be combined - e.g., /WP + BP bits protect boot sectors while leaving application sectors writable.

W25Q128JVPJQ TR Specifications

Product attributes: Attribute value

Manufacturer:: Winbond Electronics Corporation

Series:: SpiFlash®

Package/Case:: 8-WDFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Programmable:: Not Verified

Memory Type:: Non-Volatile

Memory Format:: FLASH

Technology:: FLASH - NOR

Memory Size:: 128Mbit

Memory Organization:: 16M x 8

Memory Interface:: SPI - Quad I/O, QPI, DTR

Clock Frequency:: 133 MHz

Write Cycle Time - Word, Page:: 3ms

Access Time:: -

Voltage - Supply:: 2.7V ~ 3.6V

Operating Temperature:: -40°C ~ 105°C (TA)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 8-WSON (6x5)

W25Q128JVPJQ TR FAQ

1.How can I place an order for W25Q128JVPJQ TR through Aetrix?

Please submit a Request for Quotation (RFQ) for W25Q128JVPJQ TR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for W25Q128JVPJQ TR reliable?

The price and inventory of W25Q128JVPJQ TR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for W25Q128JVPJQ TR is usually 5 days.

3.What payment methods are accepted for W25Q128JVPJQ TR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for W25Q128JVPJQ TR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for W25Q128JVPJQ TR?

W25Q128JVPJQ TR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your W25Q128JVPJQ TR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for W25Q128JVPJQ TR?

For technical support, including W25Q128JVPJQ TR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your W25Q128JVPJQ TR requirements.

6.How does Aetrix verify that W25Q128JVPJQ TR is sourced from the original manufacturer or authorized distributors?

All W25Q128JVPJQ TR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that W25Q128JVPJQ TR meets industry standards.

7.What is the process for return or replacement of W25Q128JVPJQ TR?

All W25Q128JVPJQ TR units undergo pre-shipment inspection (PSI). If there is an issue with W25Q128JVPJQ TR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The W25Q128JVPJQ TR part is unused and in its original packaging.

Return procedure for W25Q128JVPJQ TR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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