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Winbond Electronics Corporation W25Q128JVSJM
- Part No.:
- W25Q128JVSJM
- Manufacturer:
- Winbond Electronics Corporation
- Category:
- Memory
- Package:
- 8-SOIC (0.209", 5.30mm Width)
- Datasheet:
-
W25Q128JVSJM.pdf
- Description:
- IC FLASH 128MBIT SPI/QUAD 8SOIC
- Quantity:
- Payment:
- Shipping:
Inventory:2,941
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Product details
Overview
W25Q128JVSJM from Winbond is a 128M-bit (16MB) serial NOR flash memory supporting Standard/Dual/Quad SPI, QPI, and DTR read modes. It features 4KB uniform sectors, 133MHz max clock frequency, 66MB/s continuous data transfer rate, and operates from 2.7V to 3.6V with <1µA power-down current. It is used for code XIP, firmware storage, and boot image retention in microcontroller-based embedded systems.
For engineers reviewing the W25Q128JVSJM datasheet, W25Q128JVSJM pinout, W25Q128JVSJM application, or W25Q128JVSJM equivalent, key selection considerations include Quad Enable (QE) bit configuration, /HOLD vs /RESET pin availability per package, sector protection granularity, DTR timing compliance, and JEDEC SFDP register support for flexible initialization.
Technical Context
The W25Q128JVSJM implements a dual-bank architecture with 65,536 × 256-byte programmable pages and supports erase operations at 4KB sector, 32KB block, 64KB block, and full-chip levels. Its command set includes 42 standard/dual/quad/QPI/DTR instructions, with hardware write protection via /WP and /HOLD pins plus software-controlled BP2–BP0, TB, SEC, CMP, and SRP bits.
It integrates three 256-byte one-time-programmable (OTP) security registers, a 64-bit unique ID, and a JEDEC SFDP register for discoverable parameter reporting. The device enters QPI mode via 38h instruction and exits via FFh; DTR operation requires specific setup sequences and is validated only for Fast Read Dual/Quad I/O and QPI instructions.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 128 M-bit (16 MB), organized as 65,536 × 256-byte pages |
| Operating Voltage | 2.7 V to 3.6 V - enables direct interface with 3.3 V logic without level shifting |
| Max Clock Frequency | 133 MHz - supports 532 MHz equivalent quad I/O throughput for high-speed boot loading |
| Erase Granularity | 4 KB sectors (4,096 total), 32 KB blocks (2,048), 64 KB blocks (256) - allows fine-grained firmware update partitioning |
| Program/Erase Endurance | 100,000 cycles per sector - ensures long-term reliability in field-upgradable devices |
| Data Retention | 20 years at +85°C - meets industrial temperature lifecycle requirements |
| Power-Down Current | 1 µA (typ.) - minimizes standby power in battery-backed or energy-constrained systems |
| Interface Modes | Standard SPI, Dual SPI, Quad SPI, QPI, and DTR-capable read - enables flexible host controller compatibility |
Pinout & Package
W25Q128JVSJM uses an 8-pin SOIC 208-mil package (Package Code S), with pin 1 = /CS, pin 2 = DO (IO1), pin 3 = /WP (IO2), pin 4 = GND, pin 5 = DI (IO0), pin 6 = CLK, pin 7 = /HOLD or /RESET (IO3), pin 8 = VCC. The /HOLD function is active low and available only when QE = 0; when QE = 1, pin 7 becomes IO3 for Quad SPI.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| /CS (Pin 1) | Chip Select Input | Active-low enable: high = high-impedance output, low = active communication; must transition high→low after power-up to accept commands |
| DO / IO1 (Pin 2) | Data Output / Quad I/O | Unidirectional output in Standard SPI; bidirectional I/O in Dual/Quad SPI/QPI; requires QE=1 for Quad I/O use |
| /WP / IO2 (Pin 3) | Write Protect Input / Quad I/O | Hardware lock for status register writes; disabled as /WP and repurposed as IO2 when QE=1 |
| GND (Pin 4) | Ground Reference | Primary return path for VCC and all I/O signals; must be low-impedance for stable timing and noise immunity |
| DI / IO0 (Pin 5) | Data Input / Quad I/O | Unidirectional input in Standard SPI; bidirectional I/O in Dual/Quad SPI/QPI; always active for command/address entry |
| CLK (Pin 6) | Serial Clock Input | Edge-triggered timing reference for all SPI/QPI transfers; supports Mode 0 and Mode 3; DTR requires precise setup/hold alignment |
| /HOLD or /RESET (Pin 7) | Hold or Reset Input | Active-low pause signal during active /CS; configurable as /RESET only when QE=0; not available as /RESET in 8-pin SOIC with QE=1 |
| VCC (Pin 8) | Power Supply | Single 2.7–3.6 V supply; decoupling capacitor required near pin for transient current stability during program/erase |
Key Features
| Feature | Design Value |
|---|---|
| Quad Peripheral Interface (QPI) | Reduces instruction overhead by encoding multi-byte commands into single-cycle opcodes, enabling true XIP with minimal CPU intervention |
| DTR Read Support | Enables double-data-rate sampling on CLK edges for Fast Read Dual/Quad I/O and QPI, doubling effective bandwidth without increasing clock frequency |
| Uniform 4KB Sector Architecture | Allows independent firmware partitioning (e.g., bootloader, app, config) with no risk of partial-sector corruption during updates |
| Erase/Program Suspend & Resume | Permits background interrupt handling during long erase cycles (e.g., 400 ms sector erase), preserving real-time system responsiveness |
| JEDEC SFDP Register | Provides standardized, read-only parameter table for automatic host initialization - eliminates hard-coded timing constants in bootloader code |
| 64-Bit Unique Serial Number | Enables device-level traceability and secure key derivation without external EEPROM or provisioning infrastructure |
Applications
| Industrial PLC Firmware Storage | Automotive ADAS Boot Memory |
|---|---|
Use Scenario: Storing firmware images and configuration parameters in programmable logic controllers deployed in factory automation environments with wide temperature swings and EMI exposure. IC Role / Device Role / Timing Role: Non-volatile code storage with XIP capability; provides deterministic 133MHz SPI access for fast boot and runtime code fetch. Use Value: 20-year data retention at +85°C and 100K erase cycles ensure firmware integrity over 10+ year product lifecycles without refresh. | Use Scenario: Holding boot code and safety-critical calibration data for radar and camera ECUs in autonomous driving systems requiring ASIL-B compliance. IC Role / Device Role / Timing Role: Primary boot memory mapped via Quad SPI; delivers 66MB/s sustained read throughput for sub-100ms cold boot. Use Value: Hardware write protection (/WP pin + BP bits) prevents accidental overwrite of calibrated sensor offsets during field updates. |
| Medical IoT Edge Device | Smart Home Gateway Firmware |
Use Scenario: Secure storage of encrypted firmware and patient data logs in portable diagnostic equipment with battery backup and regulatory audit requirements. IC Role / Device Role / Timing Role: Trusted execution environment anchor; leverages OTP security registers and unique ID for secure boot chain binding. Use Value: Three 256-byte OTP security registers allow cryptographic key injection during manufacturing, eliminating post-deployment key management risks. | Use Scenario: Hosting upgradable Linux kernel, rootfs, and OTA update staging area in residential Wi-Fi gateways with constrained PCB space and thermal limits. IC Role / Device Role / Timing Role: High-density, low-power storage for dual-image A/B firmware partitions; supports seamless fail-safe updates. Use Value: 1µA power-down current extends battery life during brownout events; 4KB sector granularity enables atomic delta updates under 4KB size. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial NOR flash applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MX25L12833FZC-10G | 128Mb density, 104MHz max clock, no DTR support, lacks SFDP register, 8-pin SOIC only | Lower bandwidth; unsuitable for DTR-dependent high-speed boot paths or auto-configuring hosts | Select only if DTR and SFDP are unused and cost is primary constraint |
| S25FL128SAGMFI000 | 128Mb density, 133MHz clock, supports DTR and SFDP, but requires separate /RESET pin (16-pin SOIC or BGA) | Requires PCB redesign for /RESET routing; incompatible pinout with W25Q128JVSJM's 8-pin layout | Choose when dedicated hardware reset is mandatory and board layout permits 16-pin footprint |
Compared with MX25L12833FZC-10G, W25Q128JVSJM delivers higher throughput and standardized initialization via SFDP; versus S25FL128SAGMFI000, it offers identical performance in 8-pin form factor but lacks dedicated /RESET - critical for systems requiring guaranteed reset assertion independent of QE state.
Availability
W25Q128JVSJM is available at Aetrix Electronics and suitable for industrial control, automotive telematics, and medical edge device designs requiring stable component supply, long-term lifecycle assurance, and verified DTR timing compliance.
Supply support for W25Q128JVSJM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Winbond Electronics is a Taiwan-based semiconductor company specializing in specialty memory solutions, including serial NOR/NAND flash and RAM products for industrial, automotive, and computing markets.
The W25Q series targets high-reliability embedded systems needing fast, secure, and flexible non-volatile storage - optimized for XIP, firmware updates, and parameter retention across extended temperature ranges.
FAQ
What is the package type and pin count of W25Q128JVSJM?
W25Q128JVSJM uses an 8-pin SOIC 208-mil package (Package Code S). Its pinout includes /CS, DO/IO1, /WP/IO2, GND, DI/IO0, CLK, /HOLD or /RESET/IO3, and VCC. Pin 7 functions as /HOLD when QE=0 and as IO3 in Quad SPI mode; it does not provide dedicated /RESET functionality in this 8-pin variant.
Does W25Q128JVSJM support DTR (Double Transfer Rate) operation?
Yes, W25Q128JVSJM supports DTR read modes including DTR Fast Read Dual I/O (BDh), DTR Fast Read Quad I/O (EDh), and DTR Burst Read with Wrap (0Eh). DTR operation requires proper setup sequence and is validated only for specific instructions - it doubles data rate per clock cycle but demands strict AC timing compliance per the datasheet.
How is write protection implemented on W25Q128JVSJM?
W25Q128JVSJM implements dual-layer write protection: hardware via the /WP pin (active-low, disables status register writes), and software via Block Protect (BP2–BP0), Top/Bottom (TB), Sector Protect (SEC), Complement (CMP), and Status Register Protect (SRP/SRL) bits. /WP is disabled when QE=1, making software protection essential in Quad SPI configurations.
Can W25Q128JVSJM be used for execute-in-place (XIP) applications?
Yes, W25Q128JVSJM supports true XIP via Continuous Read Mode and Quad SPI/QPI interfaces. With as few as 8 clocks to address memory and wrap lengths up to 64 bytes, it enables low-overhead instruction fetch directly from flash - widely deployed in Cortex-M and RISC-V microcontrollers for boot and runtime code execution.
What is the purpose of the SFDP register in W25Q128JVSJM?
The SFDP (Serial Flash Discoverable Parameters) register in W25Q128JVSJM is a JEDEC-standardized, read-only memory map that reports device-specific timing, voltage, and command parameters. Host processors query it at startup to auto-configure SPI settings - eliminating hardcoded values and improving interoperability across firmware versions and platforms.
W25Q128JVSJM Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Winbond Electronics Corporation
- Series:
- SpiFlash®
- Package/Case:
- 8-SOIC (0.209", 5.30mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH - NOR
- Memory Size:
- 128Mbit
- Memory Organization:
- 16M x 8
- Memory Interface:
- SPI - Quad I/O, QPI, DTR
- Clock Frequency:
- 133 MHz
- Write Cycle Time - Word, Page:
- 3ms
- Access Time:
- -
- Voltage - Supply:
- 2.7V ~ 3.6V
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
W25Q128JVSJM FAQ
1.How can I place an order for W25Q128JVSJM through Aetrix?
Please submit a Request for Quotation (RFQ) for W25Q128JVSJM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for W25Q128JVSJM reliable?
The price and inventory of W25Q128JVSJM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for W25Q128JVSJM is usually 5 days.
3.What payment methods are accepted for W25Q128JVSJM?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for W25Q128JVSJM transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for W25Q128JVSJM?
W25Q128JVSJM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your W25Q128JVSJM order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for W25Q128JVSJM?
For technical support, including W25Q128JVSJM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your W25Q128JVSJM requirements.
6.How does Aetrix verify that W25Q128JVSJM is sourced from the original manufacturer or authorized distributors?
All W25Q128JVSJM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that W25Q128JVSJM meets industry standards.
7.What is the process for return or replacement of W25Q128JVSJM?
All W25Q128JVSJM units undergo pre-shipment inspection (PSI). If there is an issue with W25Q128JVSJM, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The W25Q128JVSJM part is unused and in its original packaging.
Return procedure for W25Q128JVSJM:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
W25Q128JVSJM Tags
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