My Inquiry
My Account
Winbond Electronics Corporation W25Q128JVYIQ TR
- Part No.:
- W25Q128JVYIQ TR
- Manufacturer:
- Winbond Electronics Corporation
- Category:
- Memory
- Package:
- 24-UFBGA, WLCSP
- Datasheet:
-
W25Q128JVYIQ TR.pdf
- Description:
- IC FLASH 128MBIT SPI 24WLCSP
- Quantity:
- Payment:
- Shipping:
Inventory:2,865
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
W25Q128JVYIQ TR from Winbond is a 3.3V, 128M-bit (16MB) serial NOR flash memory with Dual/Quad SPI interface, organized into 65,536 × 256-byte pages and supporting 4KB sector, 32KB/64KB block, and full-chip erase. It delivers up to 133MHz SPI clock rate (532MHz Quad I/O equivalent), <1µA power-down current, and operates across –40°C to +105°C for industrial-plus applications including boot code storage and XIP execution.
For engineers reviewing the W25Q128JVYIQ TR datasheet, W25Q128JVYIQ TR pinout, W25Q128JVYIQ TR application, or W25Q128JVYIQ TR equivalent, key selection considerations include Quad Enable (QE) bit configuration, /HOLD vs /RESET pin availability per package, 4KB sector granularity for firmware partitioning, and JEDEC SFDP register support for auto-configuration in modern SoC bootloaders.
Technical Context
The W25Q128JVYIQ TR implements a standard SPI bus with Mode 0/3 compatibility and extends functionality via configurable Dual/Quad I/O modes enabled by the non-volatile QE bit in Status Register-2. Its command set includes Fast Read Quad I/O (EBh), Quad Input Page Program (32h), and Erase/Program Suspend (75h), enabling deterministic latency control during concurrent operations.
Memory architecture features uniform 4KB sectors (4,096 total), 256 × 64KB blocks, and three 256-byte security registers with OTP locks. Write protection combines volatile/non-volatile status bits (BP2–BP0, TB, SEC, CMP), hardware /WP and /HOLD pins, and dedicated /RESET on select packages - all coordinated through the SPI command interface without external logic.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 128 M-bit (16 MB); supports full firmware images for mid-tier microcontrollers and FPGA configuration bitstreams. |
| SPI Clock Rate | Up to 133 MHz; enables 66 MB/s continuous read throughput in Quad I/O mode - sufficient for real-time audio streaming or fast boot. |
| Erase Granularity | 4 KB sectors (4,096 units); allows independent firmware update of bootloader, application, and parameter partitions without full-chip erase. |
| Endurance & Retention | 100,000 program/erase cycles per sector; >20-year data retention at +85°C - validated for industrial logging and OTA update storage. |
| Supply Voltage | 2.7 V to 3.6 V; compatible with 3.3 V LDOs and tolerant of brown-out conditions common in battery-backed systems. |
| Operating Temp | –40°C to +105°C; qualified for industrial-plus grade use in automotive ECUs, motor drives, and outdoor IoT gateways. |
| Security Features | 64-bit unique ID, SFDP register, three 256-byte OTP-lockable security registers, and individual sector lock/unlock (36h/39h) - meets basic secure boot requirements. |
Pinout & Package
W25Q128JVYIQ TR uses an 8-pad WSON 6×5-mm package (Package Code P), with exposed thermal pad. Pin functions are identical to SOIC-208-mil but in compact surface-mount form factor optimized for high-density PCB layouts.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 /CS | Chip Select Input | Active-low enable; must transition high→low before instruction acceptance; high-impedance DO during deselect. |
| 2 DO (IO1) | Data Output / Quad I/O | Unidirectional output in Standard SPI; bidirectional IO1 in Dual/Quad mode; used for Fast Read instructions. |
| 3 /WP (IO2) | Write Protect / Quad I/O | Hardware lock for status register; becomes IO2 when QE=1 - requires pull-up if unused in Quad mode. |
| 4 GND | Ground Reference | Primary return path; must be low-inductance connection to minimize noise coupling into SPI signals. |
| 5 DI (IO0) | Data Input / Quad I/O | Unidirectional input in Standard SPI; bidirectional IO0 in Dual/Quad mode; carries commands and addresses. |
| 6 CLK | Serial Clock Input | Edge-triggered timing reference; supports Mode 0/3; max 133 MHz; requires clean signal integrity for reliable Quad I/O. |
| 7 /HOLD (IO3) | Hold / Quad I/O | Pauses ongoing operation while /CS active; becomes IO3 when QE=1 - not available as /HOLD in Quad mode. |
| 8 VCC | Power Supply | 2.7–3.6 V supply; decoupling capacitor (100 nF) required within 5 mm for stable high-speed operation. |
Key Features
| Feature | Design Value |
|---|---|
| Quad SPI Interface | Enables 532 MHz equivalent bandwidth via EBh instruction; reduces boot time by >60% vs Standard SPI in XIP configurations. |
| Erase/Program Suspend | 75h/7Ah commands allow background sector erase to pause/resume during critical host operations - essential for real-time systems. |
| Individual Sector Lock | 36h/39h instructions provide per-sector write protection independent of BP bits - supports dynamic firmware partitioning. |
| JEDEC SFDP Support | 5Ah instruction returns standardized parameter table; enables automatic driver initialization in Linux U-Boot and Zephyr RTOS. |
| 64-bit Unique ID | 4Bh instruction reads factory-programmed serial number; used for device authentication, license binding, and field failure traceability. |
Applications
| Industrial Boot Memory | Firmware Update Storage |
|---|---|
|
Use Scenario: Storing bootloader and application firmware for ARM Cortex-M7-based PLC controllers operating in –40°C to +105°C environments. IC Role / Device Role / Timing Role: Primary non-volatile code storage with XIP-capable Quad SPI interface; executes directly from flash during cold start. Use Value: 4KB sector erase enables atomic firmware updates without interrupting real-time I/O scanning; 100K-cycle endurance ensures >10 years of field upgrades. |
Use Scenario: Holding differential firmware patches and rollback images in medical infusion pumps requiring FDA-compliant audit trails. IC Role / Device Role / Timing Role: Secure, versioned storage partition with individual sector lock (36h) and 64-bit UID for patch signature binding. Use Value: Three OTP-locked security registers store cryptographic keys; SFDP auto-detection simplifies driver porting across pump models. |
| Automotive Infotainment | IoT Edge Gateway |
|
Use Scenario: Caching map tile assets and voice recognition models in automotive head units with ASIL-B functional safety constraints. IC Role / Device Role / Timing Role: High-bandwidth Quad I/O memory supporting 66 MB/s streaming; integrated /RESET pin (in TFBGA variant) enables safe recovery after ECU reset. Use Value: 133 MHz SPI clock and wrap-mode continuous read (77h) reduce UI latency; -40°C to +105°C rating meets AEC-Q100 Grade 2 requirements. |
Use Scenario: Storing LoRaWAN stack binaries and sensor calibration data in battery-powered smart meter gateways deployed outdoors. IC Role / Device Role / Timing Role: Low-power memory with <1 µA deep-sleep current; sector-protected parameter storage survives frequent power cycling. Use Value: Hardware /WP pin + BP bits prevent accidental overwrite of calibration tables; 20-year data retention eliminates field recalibration needs. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial NOR flash memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MX25L12833FZNI-10G | 128 M-bit, 104 MHz max SPI clock, no Quad I/O suspend/resume, 3.0–3.6 V supply | Lacks Erase/Program Suspend (75h/7Ah); no SFDP register; only Standard/Dual SPI | Select when Quad bandwidth is unnecessary and cost sensitivity outweighs advanced feature requirements. |
| S25FL128SAGMFV001 | 128 M-bit, 133 MHz, supports Octal DTR mode, 2.7–3.6 V, includes ECC and error recovery | Includes on-die ECC and built-in error recovery; higher pin count (16-pin SOIC or BGA); larger footprint | Choose for mission-critical applications requiring guaranteed bit-error correction and extended reliability reporting. |
Compared with MX25L12833FZNI-10G and S25FL128SAGMFV001, the W25Q128JVYIQ TR offers balanced performance, industrial-plus temperature range, and Quad I/O suspend/resume - making it optimal for cost-constrained yet feature-aware embedded designs where layout space and thermal profile are critical.
Availability
W25Q128JVYIQ TR is available at Aetrix Electronics and suitable for industrial boot memory, firmware update storage, automotive infotainment caching, and IoT edge gateway data retention requiring stable component supply across long production lifecycles.
Supply support for W25Q128JVYIQ TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Winbond Electronics is a Taiwan-based semiconductor manufacturer specializing in specialty DRAM, mobile DRAM, and serial flash memory solutions for industrial, automotive, and consumer markets.
The W25Q series targets high-performance, space-constrained embedded systems requiring robust code storage, fast XIP execution, and flexible firmware update mechanisms - with emphasis on industrial-plus reliability and SPI protocol extensibility.
FAQ
What is the package type and footprint of W25Q128JVYIQ TR?
W25Q128JVYIQ TR uses an 8-pad WSON 6×5-mm package (Package Code P) with exposed thermal pad. It shares pinout compatibility with SOIC-208-mil but occupies ~35% less board area. The footprint requires solder mask defined pads and controlled thermal relief for reflow reliability - confirmed in Winbond's WSON-8 packaging specification document dated March 2021.
Does W25Q128JVYIQ TR support hardware reset, and how is it implemented?
W25Q128JVYIQ TR does not include a dedicated /RESET pin - that function is only available on SOIC-16 (F) and TFBGA (B/C) packages. For W25Q128JVYIQ TR (WSON-8), system-level reset must be handled via software using the Enable Reset (66h) and Reset Device (99h) instruction sequence, which takes ~30 µs to complete. This is documented in Section 6.4 of the March 2021 Revision H datasheet.
How is Quad SPI mode enabled on W25Q128JVYIQ TR?
Quad SPI mode on W25Q128JVYIQ TR is enabled by setting the Quad Enable (QE) bit in Status Register-2 using the Write Status Register-2 (31h) instruction. Once QE=1, pins /WP and /HOLD become IO2 and IO3 respectively. This configuration is non-volatile and persists across power cycles - verified in Section 7.1.4 and Figure 1b of the datasheet.
What is the minimum erase unit size supported by W25Q128JVYIQ TR?
W25Q128JVYIQ TR supports 4KB sector erase as its smallest erase unit, with 4,096 uniform sectors across the 128M-bit array. This granularity enables precise firmware partitioning - for example, isolating bootloader, application, and configuration sections. Sector erase is executed via the 20h instruction and takes typical 300 ms, as specified in Table 9.6 of the datasheet.
Can W25Q128JVYIQ TR be used in systems requiring JEDEC SFDP compliance?
Yes, W25Q128JVYIQ TR fully supports JEDEC JESD216B SFDP (Serial Flash Discoverable Parameters) via the 5Ah instruction. It returns a standardized 256-byte parameter table containing clock frequency limits, erase block sizes, and address width - enabling automatic driver configuration in U-Boot, Linux MTD, and Zephyr without hard-coded assumptions about memory geometry.
W25Q128JVYIQ TR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Winbond Electronics Corporation
- Series:
- SpiFlash®
- Package/Case:
- 24-UFBGA, WLCSP
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH - NOR
- Memory Size:
- 128Mbit
- Memory Organization:
- 16M x 8
- Memory Interface:
- SPI - Quad I/O, QPI
- Clock Frequency:
- 133 MHz
- Write Cycle Time - Word, Page:
- 3ms
- Access Time:
- 6 ns
- Voltage - Supply:
- 2.7V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 24-WLCSP
W25Q128JVYIQ TR FAQ
1.How can I place an order for W25Q128JVYIQ TR through Aetrix?
Please submit a Request for Quotation (RFQ) for W25Q128JVYIQ TR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for W25Q128JVYIQ TR reliable?
The price and inventory of W25Q128JVYIQ TR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for W25Q128JVYIQ TR is usually 5 days.
3.What payment methods are accepted for W25Q128JVYIQ TR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for W25Q128JVYIQ TR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for W25Q128JVYIQ TR?
W25Q128JVYIQ TR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your W25Q128JVYIQ TR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for W25Q128JVYIQ TR?
For technical support, including W25Q128JVYIQ TR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your W25Q128JVYIQ TR requirements.
6.How does Aetrix verify that W25Q128JVYIQ TR is sourced from the original manufacturer or authorized distributors?
All W25Q128JVYIQ TR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that W25Q128JVYIQ TR meets industry standards.
7.What is the process for return or replacement of W25Q128JVYIQ TR?
All W25Q128JVYIQ TR units undergo pre-shipment inspection (PSI). If there is an issue with W25Q128JVYIQ TR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The W25Q128JVYIQ TR part is unused and in its original packaging.
Return procedure for W25Q128JVYIQ TR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
W25Q128JVYIQ TR Tags
-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology
-
AT21CS01-STUM10-T
Microchip Technology
-
AT24C02C-SSHM-T
Microchip Technology
-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics
-
AT24CS02-SSHM-T
Microchip Technology
-
93LC46BT-I/OT
Microchip Technology
-
AT24C04C-SSHM-T
Microchip Technology
-
24LC01BT-I/SN
Microchip Technology
-
24AA02UIDT-I/OT
Microchip Technology
-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
