Winbond Electronics Corporation W25Q128JWBIM
- Part No.:
- W25Q128JWBIM
- Manufacturer:
- Winbond Electronics Corporation
- Category:
- Memory
- Package:
- 24-TBGA
- Datasheet:
-
W25Q128JWBIM.pdf
- Description:
- IC FLASH 128MBIT SPI 24TFBGA
- Quantity:
- Payment:

- Shipping:

Inventory:1,955
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
W25Q128JWBIM from Winbond is a 128M-bit (16MB) 1.8V serial NOR flash memory supporting Standard, Dual, and Quad SPI interfaces with up to 133MHz clock frequency and 532MHz equivalent Quad I/O throughput. It features uniform 4KB sectors, 100K program-erase cycles, 20-year data retention, and hardware write protection via /WP and /HOLD pins. It is used in embedded boot code storage, XIP execution, and firmware update storage for industrial-grade microcontrollers.
For engineers reviewing the W25Q128JWBIM datasheet, W25Q128JWBIM pinout, W25Q128JWBIM application, or W25Q128JWBIM equivalent, key selection criteria include 1.8V operation, Quad SPI XIP capability, sector-level erase flexibility, hardware write protect pin behavior, and compatibility with SOIC-208-mil (Package Code S) footprint.
Technical Context
The W25Q128JWBIM implements a SPI-compatible serial interface with Mode 0 and Mode 3 support, enabling interoperability with standard MCU SPI peripherals. Its architecture supports three operational modes: Standard SPI (DI/DO), Dual SPI (IO0/IO1), and Quad SPI (IO0–IO3), where Quad mode requires non-volatile QE bit enablement in Status Register-2.
It integrates volatile and non-volatile status register bits for block/sector protection (BP2–BP0, TB, SEC, CMP), security register locks (LB3–LB1), and configurable output driver strength (DRV1/DRV0). Erase/program suspend/resume functionality enables concurrent background operations without halting host communication.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 128 M-bit (16 MB), organized as 65,536 × 256-byte pages |
| Supply Voltage | 1.7 V to 1.95 V - enables low-power operation in 1.8V system rails |
| SPI Clock Frequency | Up to 133 MHz - delivers 532 MB/s equivalent bandwidth in Quad I/O mode |
| Erase Granularity | 4 KB sectors, 32 KB blocks, 64 KB blocks - supports fine-grained firmware partitioning |
| Endurance & Retention | 100,000 program-erase cycles; >20 years data retention at 85°C |
| Operating Temperature | −40°C to +105°C - qualified for Industrial Plus grade applications |
| Power Consumption | 1 mA active current (typ.), <1 µA power-down current (typ.) - suitable for battery-backed systems |
Pinout & Package
W25Q128JWBIM uses the 8-pin SOIC 208-mil package (Package Code S), with no dedicated /RESET pin - /HOLD pin serves dual function as IO3 in Quad mode. Pin functions are electrically defined per SPI mode and status register configuration.
| Pin | Circuit Role | Design Meaning |
|---|---|---|
| 1 /CS | Chip Select Input | Active-low enable; high-impedance DO during deselect; must transition high→low after power-up before instruction acceptance |
| 2 DO (IO1) | Data Output / Bidirectional I/O | Unidirectional output in Standard SPI; bidirectional IO1 in Dual/Quad SPI; requires QE=1 for Quad use |
| 3 /WP (IO2) | Write Protect Input / Bidirectional I/O | Hardware write lock for status register when low; becomes IO2 in Quad mode when QE=1 |
| 4 GND | Ground Reference | Primary return path for VCC and I/O signals; decoupling capacitor required near pin |
| 5 DI (IO0) | Data Input / Bidirectional I/O | Unidirectional input in Standard SPI; bidirectional IO0 in Dual/Quad SPI; rising-edge sampled |
| 6 CLK | Serial Clock Input | Edge-triggered timing reference; supports Mode 0 (CLK idle low) and Mode 3 (CLK idle high) |
| 7 /HOLD (IO3) | Hold Input / Bidirectional I/O | Pauses ongoing read/write when low and /CS active; becomes IO3 in Quad mode when QE=1; not available in Quad if held low |
| 8 VCC | Power Supply | 1.7–1.95 V supply; internal regulation ensures stable core voltage; requires local 100 nF ceramic decoupling |
Key Features
| Feature | Design Value |
|---|---|
| Quad SPI XIP Support | Enables direct code execution from flash via 133 MHz Quad I/O, eliminating RAM copy overhead for boot firmware |
| Erase/Program Suspend | Allows host to pause background erase/program and service urgent reads/writes - critical for real-time firmware updates |
| Individual Sector Lock | Per-sector (4KB) OTP-based locking via Security Registers prevents unauthorized modification of critical bootloader sections |
| 64-bit Unique ID | Factory-programmed immutable identifier used for device authentication, secure provisioning, and anti-cloning in IoT edge nodes |
| SFDP Register | Standard Flash Discovery Parameter table allows automatic host configuration of timing, voltage, and feature sets without hardcoding |
Applications
| Industrial PLC Firmware Storage | Medical Device Bootloader |
|---|---|
|
Use Scenario: Storing certified bootloader and application firmware in programmable logic controllers requiring field-upgradable, tamper-resistant storage. IC Role / Device Role / Timing Role: Primary non-volatile code storage with Quad SPI XIP capability for deterministic boot latency and secure firmware validation. Use Value: 4KB sector granularity enables atomic firmware patching; hardware /WP pin prevents accidental corruption during brown-out events. |
Use Scenario: Holding FDA-compliant boot code and calibration data in portable diagnostic equipment with strict data integrity requirements. IC Role / Device Role / Timing Role: Trusted boot source with OTP-locked security registers and 20-year data retention for life-critical parameter storage. Use Value: Unique 64-bit ID enables device-specific cryptographic key binding; -40°C to +105°C rating ensures reliability in sterilization environments. |
| Automotive ADAS Camera Module | Smart Energy Meter Firmware |
|
Use Scenario: Hosting image processing firmware and runtime configuration in automotive surround-view camera modules operating under extended temperature stress. IC Role / Device Role / Timing Role: High-speed Quad SPI interface supplies continuous frame metadata and calibration tables to SoC without DRAM buffering. Use Value: 133 MHz clock + 532 MB/s throughput meets real-time sensor fusion bandwidth; Industrial Plus grade ensures AEC-Q100 alignment. |
Use Scenario: Storing tariff tables, communication stack binaries, and tamper-evident event logs in utility-grade smart meters deployed in uncontrolled outdoor enclosures. IC Role / Device Role / Timing Role: Secure, long-life firmware repository with hardware write protection and sector-level lock for regulatory compliance data. Use Value: 100K endurance supports decades of over-the-air updates; SFDP register simplifies migration across meter generations. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial NOR flash memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MX25L12833FZC-10G | 3V supply (2.7–3.6V); no /HOLD pin in 8-pin SOIC; lacks SFDP and unique ID | Requires level-shifting in 1.8V systems; limited security features reduce suitability for certified firmware storage | Select only if existing 3V design reuse is mandatory and security features are non-critical |
| IS25LP128-JBLE | 1.8V operation; includes octal DTR support (not in W25Q128JWBIM); higher 166 MHz max clock | Enables faster future-proofing but adds complexity; pinout differs (no /WP on same pin as IO2) | Prefer for new designs targeting higher bandwidth; verify /WP routing compatibility before PCB layout |
Compared with MX25L12833FZC-10G and IS25LP128-JBLE, W25Q128JWBIM provides optimal balance of 1.8V compatibility, industrial temperature range, hardware write protection pin mapping, and mature Quad SPI ecosystem support - making it ideal for cost-sensitive, safety-aware embedded deployments where proven qualification matters more than peak speed.
Availability
W25Q128JWBIM is available at Aetrix Electronics and suitable for industrial control systems, medical diagnostics equipment, automotive camera modules, and smart energy metering applications requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for W25Q128JWBIM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Winbond Electronics is a Taiwan-based semiconductor company specializing in specialty memory solutions, including serial flash, mobile DRAM, and code storage devices for industrial and automotive markets.
The W25Q series was designed specifically for high-reliability embedded systems needing fast, secure, and flexible code and data storage - with emphasis on Quad SPI performance, robust write protection, and extended temperature operation.
FAQ
What is the package type and pin count of W25Q128JWBIM?
W25Q128JWBIM uses an 8-pin SOIC 208-mil package (Package Code S) with no dedicated /RESET pin. Pin 7 functions as /HOLD in Standard/Dual SPI mode and becomes IO3 in Quad SPI mode when the Quad Enable (QE) bit is set. This matches the JEDEC-standard SOIC-8 footprint widely supported in industrial PCB layouts.
Does W25Q128JWBIM support Quad SPI operation out of the box?
No - W25Q128JWBIM requires explicit configuration to enable Quad SPI. The non-volatile Quad Enable (QE) bit in Status Register-2 must be set via Write Status Register-2 (31h) instruction. Until then, pins /WP and /HOLD remain functional as hardware write protect and hold inputs, not as IO2 and IO3.
How does hardware write protection work on W25Q128JWBIM?
W25Q128JWBIM implements dual-layer hardware write protection: the /WP pin (Pin 3) disables status register writes when pulled low, and its effect is modulated by Status Register bits SRP and WPS. When /WP is asserted and WPS=1, individual sectors can be locked via Security Registers - providing both global and granular protection against accidental or malicious overwrite.
What is the significance of the "BIM" suffix in W25Q128JWBIM?
The "BIM" suffix in W25Q128JWBIM denotes the specific packaging and marking variant: "B" = 8-pin SOIC 208-mil, "I" = Industrial Plus grade (−40°C to +105°C), and "M" = standard reliability level with full electrical testing and traceable lot documentation - confirming suitability for mission-critical industrial deployments.
Can W25Q128JWBIM be used for Execute-in-Place (XIP) applications?
Yes - W25Q128JWBIM supports true XIP via Fast Read Quad I/O (EBh) instruction, delivering up to 532 MB/s effective bandwidth at 133 MHz clock. Its uniform 4KB sector architecture, erase/program suspend capability, and deterministic latency make it suitable for real-time XIP in microcontroller-based systems without external RAM caching.
W25Q128JWBIM Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Winbond Electronics Corporation
- Series:
- SpiFlash®
- Package/Case:
- 24-TBGA
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH - NOR
- Memory Size:
- 128Mbit
- Memory Organization:
- 16M x 8
- Memory Interface:
- SPI - Quad I/O
- Clock Frequency:
- 133 MHz
- Write Cycle Time - Word, Page:
- -, 3ms
- Access Time:
- -
- Voltage - Supply:
- 1.7V ~ 1.95V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 24-TFBGA (6x8)
W25Q128JWBIM FAQ
1.How can I place an order for W25Q128JWBIM through Aetrix?
Please submit a Request for Quotation (RFQ) for W25Q128JWBIM on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for W25Q128JWBIM reliable?
The price and inventory of W25Q128JWBIM are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for W25Q128JWBIM is usually 5 days.
3.What payment methods are accepted for W25Q128JWBIM?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for W25Q128JWBIM transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for W25Q128JWBIM?
W25Q128JWBIM orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your W25Q128JWBIM order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for W25Q128JWBIM?
For technical support, including W25Q128JWBIM datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your W25Q128JWBIM requirements.
6.How does Aetrix verify that W25Q128JWBIM is sourced from the original manufacturer or authorized distributors?
All W25Q128JWBIM products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that W25Q128JWBIM meets industry standards.
7.What is the process for return or replacement of W25Q128JWBIM?
All W25Q128JWBIM units undergo pre-shipment inspection (PSI). If there is an issue with W25Q128JWBIM, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The W25Q128JWBIM part is unused and in its original packaging.
Return procedure for W25Q128JWBIM:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
W25Q128JWBIM Tags

-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology

-
AT21CS01-STUM10-T
Microchip Technology

-
AT24C02C-SSHM-T
Microchip Technology

-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics

-
AT24CS02-SSHM-T
Microchip Technology

-
93LC46BT-I/OT
Microchip Technology

-
AT24C04C-SSHM-T
Microchip Technology

-
24LC01BT-I/SN
Microchip Technology

-
24AA02UIDT-I/OT
Microchip Technology

-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

