Winbond Electronics Corporation W25Q128JWBIQ
- Part No.:
- W25Q128JWBIQ
- Manufacturer:
- Winbond Electronics Corporation
- Category:
- Memory
- Package:
- 24-TBGA
- Datasheet:
-
W25Q128JWBIQ.pdf
- Description:
- IC FLASH 128MBIT SPI 24TFBGA
- Quantity:
- Payment:

- Shipping:

Inventory:474
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Product details
Overview
W25Q128JWBIQ from Winbond is a 1.8V, 128M-bit (16MB) serial NOR flash memory supporting Standard, Dual, and Quad SPI interfaces with up to 133MHz clock frequency, 532MHz equivalent Quad I/O throughput, and 4KB uniform sector architecture - deployed in industrial-grade embedded systems for code storage, XIP execution, and firmware parameter retention.
For engineers reviewing the W25Q128JWBIQ datasheet, W25Q128JWBIQ pinout, W25Q128JWBIQ application, or W25Q128JWBIQ equivalent, key selection criteria include Quad SPI enable (QE bit), /WP and /HOLD pin behavior in different SPI modes, 1.7–1.95V VCC operating range, -40°C to +105°C temperature grade, and package-specific /RESET availability.
Technical Context
The W25Q128JWBIQ implements a flexible SPI interface supporting Mode 0 and Mode 3 clock polarity, with configurable I/O pin mapping: DI/DO become IO0/IO1 in Dual mode, and IO0–IO3 in Quad mode upon setting the non-volatile QE bit in Status Register-2. The device integrates hardware write protection via active-low /WP and /HOLD pins, both repurposed as IO2 and IO3 respectively when QE=1.
It features three status registers (SR1–SR3) with volatile/non-volatile bits for block/sector protection (BP2–BP0, TB, SEC, CMP), security register locks (LB3–LB1), output driver strength (DRV1/DRV0), and erase/program suspend/resume capability - enabling robust firmware update sequencing and secure boot partitioning in resource-constrained microcontrollers.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Density | 128 M-bit (16 MB), organized as 65,536 × 256-byte pages |
| Supply Voltage | 1.7–1.95 V - enables low-power operation in battery-backed or energy-efficient industrial controllers |
| SPI Clock Max | 133 MHz Quad I/O - delivers 532 Mbps effective bandwidth for fast code shadowing or XIP |
| Erase Granularity | Uniform 4 KB sectors (4,096 total), 32 KB blocks (512), 64 KB blocks (256) - supports fine-grained firmware updates |
| Data Retention | >20 years - ensures long-term reliability in unattended industrial deployments |
| Endurance | 100,000 program/erase cycles per sector - suitable for frequent OTA firmware patching |
| Operating Temp | -40°C to +105°C - qualified for extended industrial and automotive under-hood applications |
| Security Features | 64-bit unique ID, SFDP register, 3×256-byte OTP-locked security registers, individual sector lock/unlock commands |
Pinout & Package
W25Q128JWBIQ is supplied in an 8-pin SOIC 208-mil package (Package Code S), with no dedicated /RESET pin - /HOLD pin serves dual function as IO3 in Quad mode. Pin functions are validated per Winbond datasheet Rev. G, Figure 1a and Section 3.3.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 /CS | Chip Select Input | Active-low enable; high-impedance DO during deselect; must transition high→low after power-up to accept instructions |
| 2 DO (IO1) | Data Output / Bidirectional I/O | Standard SPI output only; becomes bidirectional IO1 in Dual/Quad mode; requires QE=1 for Quad use |
| 3 /WP (IO2) | Write Protect Input / Bidirectional I/O | Hardware write lock for status register; repurposed as IO2 in Quad mode when QE=1 |
| 4 GND | Ground Reference | Primary return path for VCC and I/O signals; critical for noise immunity in high-speed SPI timing |
| 5 DI (IO0) | Data Input / Bidirectional I/O | Standard SPI input only; becomes bidirectional IO0 in Dual/Quad mode; required for all instruction writes |
| 6 CLK | Serial Clock Input | Edge-triggered timing source; supports Mode 0 (CLK idle low) and Mode 3 (CLK idle high) |
| 7 /HOLD (IO3) | Hold Input / Bidirectional I/O | Pauses ongoing read/write; becomes IO3 in Quad mode when QE=1; not available during Quad operation |
| 8 VCC | Power Supply | 1.7–1.95 V supply; internal regulation supports stable core voltage across industrial temp range |
Key Features
| Feature | Design Value |
|---|---|
| Quad SPI Enable (QE bit) | Non-volatile bit in Status Register-2 that reassigns /WP and /HOLD to IO2/IO3 - essential for enabling 4-line data transfer |
| Erase/Program Suspend | Allows pausing active erase or program operations to service higher-priority reads - critical for real-time interrupt handling |
| Individual Sector Lock | Per-sector 1-bit lock (via 36h/39h commands) enables immutable bootloader or calibration data partitions |
| 64-bit Unique ID | Factory-programmed read-only identifier used for device authentication and secure firmware binding |
| Output Driver Strength Control | Volatile/non-volatile DRV1/DRV0 bits adjust slew rate to match PCB trace impedance - reduces signal integrity issues at 133MHz |
| SFDP Register Support | Standard Flash Discovery Parameter table (5Ah) provides auto-configurable timing and feature parameters to host controller |
Applications
| Industrial PLC Firmware Storage | Automotive ADAS Boot Memory |
|---|---|
|
Use Scenario: Storing firmware images and configuration tables in programmable logic controllers operating continuously in factory environments. IC Role / Device Role / Timing Role: Non-volatile code storage with XIP-capable Quad SPI interface enabling direct execution of control algorithms without RAM loading delay. Use Value: 4KB sector granularity allows atomic firmware updates without disrupting live I/O scanning; 100K endurance supports decades of field upgrades. |
Use Scenario: Hosting boot code and safety-critical sensor calibration data in advanced driver-assistance systems requiring ASIL-B compliance. IC Role / Device Role / Timing Role: Secure, tamper-resistant boot memory with 64-bit unique ID and OTP-locked security registers for cryptographic key binding. Use Value: -40°C to +105°C rating ensures reliable startup in extreme ambient conditions; SFDP support simplifies host controller initialization across variants. |
| Medical Device Parameter Archive | Smart Energy Meter Firmware |
|
Use Scenario: Retaining patient-specific calibration settings and usage logs in portable diagnostic equipment with battery backup. IC Role / Device Role / Timing Role: Low-power (1µA deep power-down) persistent storage with hardware /WP protection against accidental overwrites during brown-out events. Use Value: 20-year data retention guarantees regulatory-compliant record longevity; uniform 4KB sectors simplify audit-trail logging with wear-leveling. |
Use Scenario: Storing tariff tables, communication stack binaries, and firmware patches in utility-grade smart meters deployed outdoors. IC Role / Device Role / Timing Role: Industrial-grade flash with extended temperature tolerance and robust ESD immunity for harsh metering environments. Use Value: Dual/Quad SPI flexibility enables cost-optimized MCU integration - standard SPI for legacy hosts, Quad for next-gen high-throughput modems. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial NOR flash memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MX25L12833FZC-10G | 3V supply (2.7–3.6V), no /HOLD pin in 8-pin SOIC, lacks SFDP register and OTP security registers | Requires separate voltage regulator; unsuitable for secure boot or auto-negotiated timing configurations | Select only if system already uses 3V rail and security features are unnecessary |
| IS25LP128F-JBLE | 1.8V supply, same density and Quad SPI support, but includes dedicated /RESET pin even in 8-pin SOIC variant | Enables hardware reset without package change; simplifies fail-safe recovery in safety-critical designs | Prefer when deterministic hardware reset is required and board layout allows minor footprint adjustment |
Compared with MX25L12833FZC-10G, W25Q128JWBIQ offers lower voltage operation, integrated security features, and SFDP support - while IS25LP128F-JBLE adds /RESET in compact SOIC but trades off some OTP flexibility and unique ID implementation.
Availability
W25Q128JWBIQ is available at Aetrix Electronics and suitable for industrial automation, automotive electronics, and medical device design requiring stable component supply, long-term lifecycle assurance, and guaranteed industrial temperature grade compliance.
Supply support for W25Q128JWBIQ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Winbond Electronics is a Taiwan-based semiconductor company specializing in specialty memory solutions, including SPI NOR/NAND flash, RAM, and mobile DRAM - serving industrial, automotive, and consumer markets since 1987.
The W25Q series was designed specifically for high-reliability embedded systems needing fast, secure, and low-voltage serial flash - with emphasis on XIP performance, firmware update resilience, and extended temperature operation.
FAQ
What is the supply voltage range for W25Q128JWBIQ?
The W25Q128JWBIQ operates from 1.7 V to 1.95 V - a tightly regulated 1.8V nominal range optimized for low-power industrial microcontrollers. This narrow window eliminates need for external voltage translation and ensures compatibility with modern ultra-low-power SoCs. Operation outside this range may cause undefined behavior or permanent damage. The W25Q128JWBIQ includes internal voltage monitoring that disables writes below threshold to prevent corruption.
Does W25Q128JWBIQ support hardware reset in its 8-pin SOIC package?
No, W25Q128JWBIQ in the 8-pin SOIC 208-mil package (S-code) does not include a dedicated /RESET pin - the /HOLD pin serves dual function as IO3 in Quad mode. Hardware reset is only available in 16-pin SOIC (F-code) and TFBGA (B/C-code) packages. For W25Q128JWBIQ in SOIC-8, software reset (66h + 99h) is the only reset method supported.
How is Quad SPI enabled on W25Q128JWBIQ?
Quad SPI is enabled by setting the Quad Enable (QE) bit in Status Register-2 using the Write Status Register-2 (31h) instruction. Once QE=1, the /WP and /HOLD pins become IO2 and IO3 respectively. This change is non-volatile unless cleared. The W25Q128JWBIQ must be configured this way before issuing Quad I/O commands like EBh (Fast Read Quad I/O); otherwise, those instructions will not function.
What package type is used for W25Q128JWBIQ?
W25Q128JWBIQ is packaged in an 8-pin SOIC 208-mil (Package Code S), measuring 5.3 mm × 5.3 mm with 1.27 mm pitch. This industry-standard footprint ensures drop-in compatibility with existing PCB layouts designed for legacy SPI flash devices. The marking "W25Q128JWBIQ" appears on the top surface, with date code and lot traceability per JEDEC standards.
Can W25Q128JWBIQ be used for execute-in-place (XIP) applications?
Yes, W25Q128JWBIQ supports XIP via Dual and Quad SPI interfaces - especially Fast Read Quad I/O (EBh) delivering up to 532 Mbps throughput. Its 4KB uniform sector architecture allows precise mapping of executable code segments, while erase/program suspend enables real-time interrupt servicing during background updates. The W25Q128JWBIQ's low latency and deterministic timing make it suitable for hard real-time XIP in Cortex-M7 and RISC-V systems.
W25Q128JWBIQ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Winbond Electronics Corporation
- Series:
- SpiFlash®
- Package/Case:
- 24-TBGA
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- FLASH
- Technology:
- FLASH - NOR
- Memory Size:
- 128Mbit
- Memory Organization:
- 16M x 8
- Memory Interface:
- SPI - Quad I/O
- Clock Frequency:
- 133 MHz
- Write Cycle Time - Word, Page:
- -, 3ms
- Access Time:
- -
- Voltage - Supply:
- 1.7V ~ 1.95V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 24-TFBGA (6x8)
W25Q128JWBIQ FAQ
1.How can I place an order for W25Q128JWBIQ through Aetrix?
Please submit a Request for Quotation (RFQ) for W25Q128JWBIQ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for W25Q128JWBIQ reliable?
The price and inventory of W25Q128JWBIQ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for W25Q128JWBIQ is usually 5 days.
3.What payment methods are accepted for W25Q128JWBIQ?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for W25Q128JWBIQ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for W25Q128JWBIQ?
W25Q128JWBIQ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your W25Q128JWBIQ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for W25Q128JWBIQ?
For technical support, including W25Q128JWBIQ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your W25Q128JWBIQ requirements.
6.How does Aetrix verify that W25Q128JWBIQ is sourced from the original manufacturer or authorized distributors?
All W25Q128JWBIQ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that W25Q128JWBIQ meets industry standards.
7.What is the process for return or replacement of W25Q128JWBIQ?
All W25Q128JWBIQ units undergo pre-shipment inspection (PSI). If there is an issue with W25Q128JWBIQ, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The W25Q128JWBIQ part is unused and in its original packaging.
Return procedure for W25Q128JWBIQ:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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